公开(公告)号：US20250078895A1

公开(公告)日：2025-03-06

申请号：US18727223

申请日：2023-01-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hidefumi RIKIMARU ,  Yoshiyuki KUROKAWA ,  Satoru OHSHITA

IPC: G11C11/405 ,  G11C11/4096 ,  G11C11/54 ,  H10B12/00

Abstract: An operation method of a semiconductor device that performs data writing and correction processing is provided. The operation method is for a semiconductor device including a control circuit, a first circuit, a second circuit, a wiring, a cell, and a converter circuit. In the operation method, first, the control circuit transmits, to the first circuit, a first signal corresponding to the value of first data. Next, the first circuit outputs, to the wiring, a first current with an amount corresponding to the first signal. Moreover, the cell retains a first potential corresponding to the amount of first current. Then, the cell makes a second current corresponding to the first potential flow from the wiring, and the converter circuit outputs a second signal corresponding to the amount of second current. Next, the second circuit obtains a difference value between a value corresponding to the second signal and the value of the first data. If the difference value is 0, the operation is terminated. If the difference value is not 0, the control circuit generates an update value obtained by adding the difference value to a value corresponding to the first signal previously transmitted. The first circuit obtains the first signal corresponding to the update value and outputs the updated first current to the cell.

公开(公告)号：US20240234310A1

公开(公告)日：2024-07-11

申请号：US18560959

申请日：2022-05-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Kazuki TSUDA ,  Kouhei TOYOTAKA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU ,  Hideki UOCHI

IPC: H01L23/528 ,  H01L29/24

CPC classification number: H01L23/528 ,  H01L29/24

Abstract: A novel semiconductor device is provided. In reservoir computing using an input layer, a reservoir layer, and an output layer, variation in threshold voltage between transistors is used as a weight used for product arithmetic processing. Two transistors are provided in one product arithmetic circuit and data u is supplied to gates of the two transistors. Drain current of each of the transistors is determined by the data u and the threshold voltage of the transistor. The difference between the drain currents corresponds to a product arithmetic result. The difference between the drain currents is converted into voltage to be output. A plurality of product arithmetic circuits are connected in parallel to form a product-sum arithmetic circuit.

公开(公告)号：US20230353163A1

公开(公告)日：2023-11-02

申请号：US18018965

申请日：2021-07-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro KANEMURA ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Kazuki TSUDA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: G09G3/3233 ,  H03M1/46

CPC classification number: H03M1/46 ,  G09G3/3233 ,  H03K5/2472

Abstract: A novel semiconductor device is provided. An analog signal is converted into a digital signal using a comparison portion comparing two current values, a control portion, and a current output digital-analog conversion portion. The control portion has a function of generating a sign bit showing a magnitude relation between the two current values, a function of converting a difference between the two current values into a digital signal by successive approximation, and a function of outputting the sign bit and the digital signal.

公开(公告)号：US20220344334A1

公开(公告)日：2022-10-27

申请号：US17762473

申请日：2020-09-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru OHSHITA ,  Hitoshi KUNITAKE ,  Kazuki TSUDA

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.

公开(公告)号：US20220293049A1

公开(公告)日：2022-09-15

申请号：US17686796

申请日：2022-03-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi GODO ,  Yoshiyuki KUROKAWA ,  Kazuki TSUDA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: G09G3/3208 ,  H01L27/32

Abstract: A semiconductor device with a high driving speed is provided. The semiconductor device includes first to fourth cells, a converter circuit, and first to fourth wirings. The first and second cells make a first current and a second current each corresponding to the product of first data and second data flow in the first wiring and the second wiring, respectively. The third and fourth cells make base currents in the same amount flow in the first and second wirings. The converter circuit outputs, from an output terminal thereof, a voltage corresponding to the differential current between the sum of the first current and the base current flowing in the first wiring and the sum of the second current and the base current flowing in the second wiring.

公开(公告)号：US20240237374A9

公开(公告)日：2024-07-11

申请号：US18278199

申请日：2022-02-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi GODO ,  Yoshiyuki KUROKAWA ,  Kouhei TOYOTAKA ,  Kazuki TSUDA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: H10K39/34 ,  G06F3/01 ,  G09G3/3208 ,  H10K59/65

CPC classification number: H10K39/34 ,  G06F3/013 ,  G09G3/3208 ,  H10K59/65 ,  G09G2330/021 ,  G09G2354/00 ,  G09G2360/14

Abstract: An electronic device having an eye tracking function is provided. The electronic device includes a display device and an optical system. The display device includes a first light-emitting element, a second light-emitting element, a sensor portion, and a driver circuit portion. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light or visible light. The second light-emitting element has a function of emitting light of a color different from that of light emitted from the first light-emitting element. When the first light-emitting element emits infrared light, the light-receiving element has a function of detecting the infrared light that is emitted from the first light-emitting element and reflected by an eyeball of a user. When the first light-emitting element emits visible light, the light-receiving element has a function of detecting the visible light that is emitted from the first light-emitting element and reflected by the eyeball of the user. The first light-emitting element and the second light-emitting element are placed in one layer. The layer where the first light-emitting element and the second light-emitting element are positioned overlaps with the sensor portion.

公开(公告)号：US20240231756A9

公开(公告)日：2024-07-11

申请号：US18278451

申请日：2022-02-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Kazuki TSUDA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: G06F7/523 ,  G06F7/50 ,  G09G3/3208 ,  G11C11/405 ,  H10B12/00 ,  H10K59/121

CPC classification number: G06F7/523 ,  G06F7/50 ,  G09G3/3208 ,  G11C11/405 ,  H10B12/00 ,  H10K59/1213 ,  H10K59/1216

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.

公开(公告)号：US20230352090A1

公开(公告)日：2023-11-02

申请号：US17791326

申请日：2020-12-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuki TSUDA ,  Hiromichi GODO ,  Satoru OHSHITA ,  Hitoshi KUNITAKE ,  Satoru OKAMOTO

IPC: G11C16/04 ,  H01L29/786 ,  H01L23/528 ,  H10B43/10 ,  H10B43/35 ,  H10B43/27

CPC classification number: G11C16/0483 ,  H01L29/7869 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/35 ,  H10B43/27

Abstract: A highly reliable memory device is provided. The memory device includes a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor. At least third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order on an inner surface of the opening. The seventh conductor is provided between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.

公开(公告)号：US20230317176A1

公开(公告)日：2023-10-05

申请号：US18188678

申请日：2023-03-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: G11C16/26 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/10

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes memory layers and a driver circuit layer. The memory layers are stacked over the driver circuit layer and each include a memory cell array including a plurality of memory cells. Writing or reading of data to or from one of the memory cells is controlled with a write word line, a read word line, a write bit line, and a read bit line. The driver circuit layer includes a driver circuit portion configured to drive the write word line, the read word line, the write bit line, and the read bit line; and an arithmetic circuit portion. The driver circuit portion includes a plurality of driver circuits configured to control data writing or reading on the memory cell array basis. The arithmetic circuit portion is a circuit configured to perform arithmetic processing using the data retained in the memory cell array provided in each of the memory layers and read through the driver circuit portion.

公开(公告)号：US20220375956A1

公开(公告)日：2022-11-24

申请号：US17772280

申请日：2020-11-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Satoru OHSHITA ,  Kazuki TSUDA ,  Tatsuya ONUKI

IPC: H01L27/11573 ,  H01L27/11582 ,  G11C16/08

Abstract: A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.