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    Display Device
    12.
    发明申请
    Display Device 审中-公开
    显示设备

    公开(公告)号：US20140285410A1

    公开(公告)日：2014-09-25

    申请号：US14298292

    申请日：2014-06-06

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshifumi Tanada

    IPC: G09G3/30

    CPC classification number: H01L27/124 ,  G09G3/30 ,  G09G3/32 ,  G09G2300/0404 ,  G09G2300/0426 ,  G09G2300/0809 ,  G09G2320/0233 ,  G09G2320/0242 ,  G09G2330/02 ,  H01L27/15 ,  H01L27/156 ,  H01L27/3211 ,  H01L27/3262 ,  H01L27/3276 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A display device in which the current load of wirings are distributed and display variations due to voltage drop are suppressed. An active matrix display device of the invention comprises a first current input terminal, a second current input terminal, and a plurality of current supply lines extending parallel to each other. Each current supply line is connected to a plurality of driving transistors in a line. One end of each current supply line is connected to the first current input terminal via a first wiring intersecting with the current supply lines, and the other end thereof is connected to the second current input terminal via a second wiring intersecting with the current supply lines. Accordingly, a current is supplied to each current supply line from both the first and. the second current input terminals. The first and the second current input terminals are provided separately from each other.

    Abstract translation: 布线的电流负载分布的显示装置和由于电压降引起的显示变化被抑制。 本发明的有源矩阵显示装置包括第一电流输入端子，第二电流输入端子以及彼此平行延伸的多个电流供给线路。 每个电源线连接到一行中的多个驱动晶体管。 每个电源线的一端经由与电流供给线相交的第一布线连接到第一电流输入端，并且其另一端经由与电流线相交的第二布线连接到第二电流输入端。 因此，从第一和第二电流输入端子向每个电流供给线路提供电流。 第一和第二电流输入端子彼此分开设置。

    SEMICONDUCTOR DEVICE
    13.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140159045A1

    公开(公告)日：2014-06-12

    申请号：US14180415

    申请日：2014-02-14

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

    IPC: H01L29/786

    CPC classification number: H01L29/786 ,  H03K19/01714 ,  H03K19/01721

    Abstract: There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node α into a floating state. When the node α is in the floating state, a potential of the node α is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD−GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

    Abstract translation: 提供了一种半导体器件，其中可以通过仅使用一种导电类型的TFT构成电路并且可以正常获得输出信号的电压振幅来减小制造步骤。 电容（205）设置在连接到输出节点的TFT（203）的栅极和源极之间，并且由TFT（201）和（202）形成的电路具有使节点α成为浮置状态的功能 。 当节点α处于浮置状态时，通过使用TFT（203）通过电容（205）的栅源电容耦合，使节点α的电位高于VDD，因此具有VDD的幅度的输出信号 通常可以获得-GND，而不会由于TFT的阈值引起振幅衰减。

    Semiconductor device outputting reference voltage
    14.
    发明授权
    Semiconductor device outputting reference voltage 有权

    公开(公告)号：US11316478B2

    公开(公告)日：2022-04-26

    申请号：US16783306

    申请日：2020-02-06

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kei Takahashi ,  Yoshifumi Tanada

    IPC: H03F1/02 ,  G05F1/46 ,  H03F3/45 ,  G05F1/56 ,  H03F1/34 ,  H02M3/156

    Abstract: Power consumption of a signal processing circuit is reduced. Further, power consumption of a semiconductor device including the signal processing circuit is reduced. The signal processing circuit includes a reference voltage generation circuit, a voltage divider circuit, an operational amplifier, a bias circuit for supplying bias current to the operational amplifier, and first and second holding circuits. The first holding circuit is connected between the reference voltage generation circuit and the bias circuit. The second holding circuit is connected between the voltage divider circuit and a non-inverting input terminal of the operational amplifier. Reference voltage from the reference voltage generation circuit and reference voltage from the voltage divider circuit can be held in the first and second holding circuits, respectively, so that the reference voltage generation circuit can stop operating. Thus, power consumption of the reference voltage generation circuit can be reduced.

    Semiconductor Device and Method of Driving the Semiconductor Device
    15.
    发明申请
    Semiconductor Device and Method of Driving the Semiconductor Device 有权

    公开(公告)号：US20220123097A1

    公开(公告)日：2022-04-21

    申请号：US17467616

    申请日：2021-09-07

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hajime Kimura ,  Yoshifumi Tanada

    IPC: H01L27/32 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3283 ,  G09G3/3291 ,  G09G3/20 ,  G09G3/30 ,  G09G3/36

    Abstract: Display irregularities in light emitting devices, which develop due to dispersions per pixel in the threshold value of TFTs for supplying electric current to light emitting elements, are obstacles to increasing the image quality of the light emitting devices. An electric potential in which the threshold voltage of a TFT (105) is either added to or subtracted from the electric potential of a reset signal line (110) is stored in capacitor means (108). A voltage, in which the corresponding threshold voltage is added to an image signal, is applied to a gate electrode of a TFT (106). TFTs within a pixel are disposed adjacently, and dispersion in the characteristics of the TFTs does not easily develop. The threshold value of to the TFT (105) is thus cancelled, even if the threshold values of the TFTs (106) differ per pixel, and a predetermined drain current can be supplied to an EL element (109).

    Semiconductor device and method of driving the semiconductor device
    16.
    发明授权
    Semiconductor device and method of driving the semiconductor device 有权

    公开(公告)号：US10355068B2

    公开(公告)日：2019-07-16

    申请号：US15262192

    申请日：2016-09-12

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hajime Kimura ,  Yoshifumi Tanada

    IPC: H01L27/32 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3283 ,  G09G3/3291 ,  G09G3/20 ,  G09G3/30 ,  G09G3/36 ,  G09G3/3258 ,  G09G3/3275

    Abstract: Display irregularities in light emitting devices, which develop due to dispersions per pixel in the threshold value of TFTs for supplying electric current to light emitting elements, are obstacles to increasing the image quality of the light emitting devices. An electric potential in which the threshold voltage of a TFT (105) is either added to or subtracted from the electric potential of a reset signal line (110) is stored in capacitor means (108). A voltage, in which the corresponding threshold voltage is added to an image signal, is applied to a gate electrode of a TFT (106). TFTs within a pixel are disposed adjacently, and dispersion in the characteristics of the TFTs does not easily develop. The threshold value of the TFT (105) is thus cancelled, even if the threshold values of the TFTs (106) differ per pixel, and a predetermined drain current can be supplied to an EL element (109).

    Pulse output circuit and semiconductor device
    20.
    发明授权
    Pulse output circuit and semiconductor device 有权

    公开(公告)号：US09742378B2

    公开(公告)日：2017-08-22

    申请号：US13922685

    申请日：2013-06-20

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshifumi Tanada ,  Manabu Sato ,  Hiroyuki Miyake ,  Toshinari Sasaki ,  Kenichi Okazaki ,  Junichi Koezuka ,  Shunpei Yamazaki

    IPC: H03K3/01 ,  G11C19/28 ,  G09G3/36

    CPC classification number: H03K3/01 ,  G09G3/3688 ,  G11C19/28

    Abstract: A highly reliable semiconductor device in which a shift in threshold voltage of a transistor due to deterioration can be inhibited is provided. A pulse output circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. A clock signal is supplied to a drain of the first transistor. A first power supply potential is applied to a source of the second transistor, and a drain of the second transistor is connected to the drain of the first transistor. A second power supply potential is applied to a drain of the third transistor. The first power supply potential is applied to a source of the fourth transistor, and a drain of the fourth transistor is connected to the drain of the third transistor. The first power supply potential is applied to a source of the fifth transistor, and a drain of the fifth transistor is connected to a gate of the third transistor. One of a source and a drain of the sixth transistor is connected to the drain of the first transistor, and the other of the source and the drain of the sixth transistor is connected to the gate of the third transistor. The first transistor and the third transistor include back gates connected to each other. The first to sixth transistors have the same conductivity type.

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