公开(公告)号：US11099814B2

公开(公告)日：2021-08-24

申请号：US15729150

申请日：2017-10-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shintaro Harada ,  Yoshiyuki Kurokawa ,  Takeshi Aoki

IPC: G06F7/544 ,  G06N3/063 ,  H01L29/786 ,  G06N3/04

Abstract: A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor. A voltage between the first terminal and the second gate of the transistor is held in the capacitor, whereby a change in source-drain current of the transistor can be suppressed.

公开(公告)号：US11043186B2

公开(公告)日：2021-06-22

申请号：US15792235

申请日：2017-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Yoshiyuki Kurokawa

IPC: G09G5/10 ,  H04L27/18 ,  H04L27/32 ,  H04L5/06 ,  H04L27/02 ,  H04L27/26 ,  G02F1/1335 ,  G02F1/13357 ,  G02F1/1343 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786

Abstract: A method for transmitting image data to a display device at high speed is provided. Image data to be transmitted is input to a phase modulation portion, and is mixed with a high-frequency carrier wave. The carrier wave is modulated with a technique of phase-shift keying, and output to a transmission line determined in consideration of the transmission characteristics of the high-frequency wave. A phase regulating portion of the phase modulation portion has a function of adjusting the amount of change in phase with the use of an electric signal. A phase demodulation portion beyond the transmission line demodulates the modulated carrier wave and extracts the image data. The multi-bit image data can be transmitted by the technique of the phase-shift keying. The high-speed transmission enables serial conversion of the original image data and decreases the number of transmission lines.

公开(公告)号：US11018161B2

公开(公告)日：2021-05-25

申请号：US16471962

申请日：2018-01-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kei Takahashi ,  Yoshiyuki Kurokawa

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  G09G3/36 ,  H01L29/66 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/133 ,  G09G3/20

Abstract: A display device that is suitable for increasing its size is provided.
The display device includes first to third wirings, a first transistor, first to third conductive layers, and a first pixel electrode; the first wiring extends in a first direction and intersects with the second and the third wirings; the second and the third wirings each extend in a second direction intersecting with the first direction; a gate of the first transistor is electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring through the first to the third conductive layers; the second conductive layer includes a region overlapping with the third wiring; the first conductive layer, the third conductive layer, and the first pixel electrode contain the same material; the first wiring and the second conductive layer contain the same material; the first wiring is supplied with a selection signal; and the second and the third wirings are supplied with different signals.

公开(公告)号：US10924090B2

公开(公告)日：2021-02-16

申请号：US16511215

申请日：2019-07-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hajime Kimura ,  Yoshiyuki Kurokawa

IPC: H03K3/037 ,  G06N3/04 ,  G11C11/16 ,  G11C13/00

Abstract: A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.

公开(公告)号：US10922605B2

公开(公告)日：2021-02-16

申请号：US15296566

申请日：2016-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: G06N3/06 ,  G06N3/063 ,  G11C11/24 ,  G11C11/54 ,  G11C27/00

Abstract: A neuron circuit can switch between two functions: as an input neuron circuit, and as a hidden neuron circuit. An error circuit can switch between two functions: as a hidden error circuit, and as an output neuron circuit. A switching circuit is configured to be capable of changing the connections between the neuron circuit, a synapse circuit, and the error circuit. The synapse circuit includes an analog memory that stores data that corresponds to the connection strength between the input neuron circuit and the hidden neuron circuit or between the hidden neuron circuit and the output neuron circuit, a writing circuit that changes the data in the analog memory, and a weighting circuit that weights an input signal in reaction to the data of the analog memory and outputs the weighted output signal. The analog memory includes a transistor comprising an oxide semiconductor with extremely low off-state current.

公开(公告)号：US10916573B2

公开(公告)日：2021-02-09

申请号：US16738350

申请日：2020-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: H01L27/146 ,  H01L27/12 ,  H01L29/786 ,  H04N5/232 ,  H04N5/335 ,  H04N5/374 ,  H01L31/032 ,  G01J1/44

Abstract: A semiconductor device including photosensor capable of imaging with high resolution is disclosed. The semiconductor device includes the photosensor having a photodiode, a first transistor, and a second transistor. The photodiode generates an electric signal in accordance with the intensity of light. The first transistor stores charge in a gate thereof and converts the stored charge into an output signal. The second transistor transfers the electric signal generated by the photodiode to the gate of the first transistor and holds the charge stored in the gate of the first transistor. The first transistor has a back gate and the threshold voltage thereof is changed by changing the potential of the back gate.

公开(公告)号：US10885877B2

公开(公告)日：2021-01-05

申请号：US16465301

申请日：2018-01-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kurokawa

IPC: G06N3/08 ,  G09G5/14 ,  G06N3/063 ,  G09G3/20 ,  G09G3/22 ,  G09G3/36

Abstract: A novel semiconductor device or display system is provided. The display system includes a correction circuit having a function of correcting an image signal by utilizing artificial intelligence. Specifically, learning by an artificial neural network enables the correction circuit to correct an image signal so as to alleviate the image discontinuity. Then, by making an inference (recognition) utilizing the artificial neural network which has finished the learning, the image signal is corrected and compensation for the image discontinuity can be made. In this manner, the junction can be inconspicuous on the displayed image, improving the quality of a high-resolution image.

公开(公告)号：US10650727B2

公开(公告)日：2020-05-12

申请号：US15718289

申请日：2017-09-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: G09G3/20 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1335 ,  G06F1/3218 ,  G06F1/3234 ,  G09G3/3275 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1333 ,  G09G3/36

Abstract: An object is to provide a semiconductor device with low power consumption. The semiconductor device includes a controller, a register, and an image processing portion. The image processing portion has a function of taking image data from a frame memory and a parameter from the register and processing the image data by using the parameter. The frame memory has a function of retaining the image data while power supply is stopped. The register has a function of retaining the parameter while power supply is stopped. The controller controls power supply to the register, the frame memory, and the image processing portion. The register includes first and second scan chain registers. The first scan chain register stores a parameter related to a first display region. The second scan chain register stores a parameter related to a second display region. A parameter is changed by loading of data of the first or second scan chain register.

公开(公告)号：US10609404B2

公开(公告)日：2020-03-31

申请号：US16371174

申请日：2019-04-01

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kurokawa

IPC: H03K19/173 ,  H04N11/02 ,  H04N19/44 ,  H04N19/42 ,  H04N19/436

Abstract: Power consumption of a decoder is reduced. The decoder includes an FPGA. The FPGA performs at least one processing to decode the data. In the case where the data has first resolution, an input data signal of the FPGA is a binary signal and a clock frequency of the FPGA is a first frequency. In the case where the resolution of the data is lower than the first resolution, the input data signal of the FPGA is a pulse signal and the FPGA operates at a second frequency which is lower than the first frequency. The FPGA operates at the first clock frequency in the case of decoding 8K data and the FPGA operates at the second clock frequency in the case of decoding 4K or 2K data.

公开(公告)号：US10564698B2

公开(公告)日：2020-02-18

申请号：US15677181

申请日：2017-08-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki Okamoto ,  Yoshiyuki Kurokawa

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/42 ,  G11C11/40 ,  H03K19/0175

Abstract: A method for controlling power supply in a semiconductor device including a CPU and a PLD which can hold data even in an off state is provided. The semiconductor device includes a processor, a programmable logic device, and a state control circuit. The programmable logic device includes a first nonvolatile memory circuit and has a function of holding data obtained by arithmetic processing of the programmable logic device when it is turned off. The state control circuit obtains data on the amount of a task performed by the programmable logic device in accordance with an operation of the processor. The programmable logic device detects the state of progress of the task and outputs a signal to the state control circuit. The state control circuit monitors the amount of the task and the state of progress of the task and turns off the programmable logic device when the task is completed.