公开(公告)号：US20160379719A1

公开(公告)日：2016-12-29

申请号：US15038747

申请日：2014-08-26

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Sumio KATOH ,  Naoki UEDA

IPC: G11C17/18 ,  H01L27/112 ,  H01L29/24 ,  G11C17/16 ,  H01L29/786

CPC classification number: G11C17/18 ,  G02F1/13452 ,  G02F1/1368 ,  G02F2201/123 ,  G11C13/0007 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C19/28 ,  G11C2213/53 ,  H01L27/1052 ,  H01L27/11206 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device (1001) includes: a memory cell; and a writing control circuit (107), wherein the memory cell includes a memory transistor (10A) which has an active layer (7A), the active layer (7A) including a metal oxide, the memory transistor (10A) is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs, and the writing control circuit (107) is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode such that Vgs≧Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor (10A) and Vds is a drain-source voltage of the memory transistor (10A), whereby writing in the memory transistor (10A) is performed.

Abstract translation: 半导体器件（1001）包括：存储单元; 和写控制电路（107），其中存储单元包括具有有源层（7A）的存储晶体管（10A），所述有源层（7A）包括金属氧化物，所述存储晶体管（10A）是晶体管， 能够从漏极电流Ids取决于栅极 - 源极电压Vgs到漏极电流Ids不依赖于栅极 - 源极电压Vgs的电阻状态的半导体状态不可逆地改变，并且写入控制电路（107 ）被配置为控制施加到漏极，源电极和栅电极的电压，使得V s = Vds + Vth，其中Vth是存储晶体管（10A）的阈值电压，并且Vds是漏极 - 源极电压 存储晶体管（10A），由此执行对存储晶体管（10A）的写入。

公开(公告)号：US20160181291A1

公开(公告)日：2016-06-23

申请号：US14910454

申请日：2014-07-24

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Sumio KATOH ,  Naoki UEDA

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/3248 ,  H01L29/41733 ,  H01L29/78606 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device (100A) includes a first metal layer (12) including a gate electrode (12g); a gate insulating layer (14) formed on the first metal layer; an oxide semiconductor layer (16) formed on the gate insulating layer; a second metal layer (18) formed on the oxide semiconductor layer; an interlayer insulating layer (22) formed on the second metal layer; and a transparent electrode layer (TE) including a transparent conductive layer (Tc). The oxide semiconductor layer includes a first portion (16a) and a second portion (16b) extending while crossing an edge of the gate electrode. The second metal layer includes a source electrode (18s) and a drain electrode (18d). The interlayer insulating layer does not include an organic insulating layer. The interlayer insulating layer includes a contact hole (22a) formed so as to overlap the second portion and an end of the drain electrode that is closer to the second portion. The transparent conductive layer (Tc) is in contact with the end of the drain electrode and the second portion of the oxide semiconductor layer in the contact hole.

Abstract translation: 半导体器件（100A）包括包括栅电极（12g）的第一金属层（12） 形成在所述第一金属层上的栅极绝缘层（14） 形成在所述栅极绝缘层上的氧化物半导体层（16） 形成在所述氧化物半导体层上的第二金属层（18） 形成在所述第二金属层上的层间绝缘层（22） 和包含透明导电层（Tc）的透明电极层（TE）。 氧化物半导体层包括在与栅电极的边缘交叉的同时延伸的第一部分（16a）和第二部分（16b）。 第二金属层包括源极（18s）和漏电极（18d）。 层间绝缘层不包括有机绝缘层。 层间绝缘层包括形成为与第二部分重叠的接触孔（22a）和漏电极的靠近第二部分的端部。 透明导电层（Tc）与漏电极的端部和接触孔中的氧化物半导体层的第二部分接触。

公开(公告)号：US20190081076A1

公开(公告)日：2019-03-14

申请号：US16081502

申请日：2017-02-28

Applicant: Sharp Kabushiki Kaisha

Inventor： Kuniaki OKADA ,  Seiichi UCHIDA ,  Naoki UEDA ,  Takahiro SASAKI

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1343

Abstract: An array substrate (thin film transistor substrate) 11b includes a source line (line) 20, a TFT (thin film transistor) 17 including a plurality of electrodes 17a, 17b, and 17c, and a line connector 31 made of light-transmitting conductive material and connected to the source line 20. At least a portion of the line connector 31 includes one of electrodes 17a, 17b, and 17c.

公开(公告)号：US20160260750A1

公开(公告)日：2016-09-08

申请号：US15028238

申请日：2014-09-02

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Naoki UEDA ,  Sumio KATOH

IPC: H01L27/12 ,  G02F1/1368 ,  H01L29/423 ,  H01L45/00 ,  H01L29/786 ,  H01L29/24

CPC classification number: H01L27/1255 ,  G02F1/1368 ,  H01L27/088 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/147 ,  H01L2029/42388

Abstract: A semiconductor device (1001) includes: a first transistor (10A) having a first channel length L1 and a first channel width W1; and a second transistor (10B) having a second channel length L2 and a second channel width W2, wherein the first transistor (10A) and the second transistor (10B) include an active layer formed from a common oxide semiconductor film, the first transistor (10A) is a memory transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Isd depends on a gate voltage Vg to a resistor state where the drain current Isd does not depend on the gate voltage Vg, and the first channel length L1 is smaller than the second channel length L2.

Abstract translation: 半导体器件（1001）包括：第一晶体管（10A），具有第一沟道长度L1和第一沟道宽度W1; 和具有第二沟道长度L2和第二沟道宽度W2的第二晶体管（10B），其中第一晶体管（10A）和第二晶体管（10B）包括由公共氧化物半导体膜形成的有源层，第一晶体管 10A）是能够从漏极电流Isd取决于栅极电压Vg到漏极电流Isd不依赖于栅极电压Vg的电阻状态的半导体状态不可逆地改变的存储晶体管，并且第一通道 长度L1小于第二通道长度L2。

公开(公告)号：US20160190181A1

公开(公告)日：2016-06-30

申请号：US14650681

申请日：2013-12-02

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Naoki UEDA ,  Akihiro ODA ,  Hirohiko NISHIKI ,  Tohru OKABE

IPC: H01L27/12 ,  H01L29/786 ,  G09G3/36 ,  H01L29/45 ,  H01L29/417 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L27/1248 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0286 ,  G11C19/287 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor device includes: a plurality of thin film transistors including a gate electrode, a gate dielectric layer, a semiconductor layer formed on the gate dielectric layer, and a source electrode and a drain electrode provided on the semiconductor layer; a source metal layer including a global line which supplies a common signal to the plurality of thin film transistors, the global line being made of the same electrically conductive film as the source electrode and drain electrode; and a dielectric protection layer covering the plurality of thin film transistors and the source metal layer. The source metal layer includes a lower layer and an upper layer stacked on a portion of the lower layer. The global line has a first layer structure including the lower layer and the upper layer, and at least a portion of each source electrode and of each drain electrode that is located on the semiconductor layer has a second layer structure including the lower layer but not including the upper layer.

Abstract translation: 半导体器件包括：多个薄膜晶体管，包括栅极电极，栅极电介质层，形成在栅极电介质层上的半导体层，以及设置在半导体层上的源电极和漏电极; 源极金属层，包括向多个薄膜晶体管提供公共信号的全局线，全局线由与源电极和漏电极相同的导电膜制成; 以及覆盖多个薄膜晶体管和源极金属层的介电保护层。 源极金属层包括层叠在下层的一部分上的下层和上层。 全局线具有包括下层和上层的第一层结构，并且位于半导体层上的每个源电极和每个漏电极的至少一部分具有包括下层但不包括的第二层结构 上层。