公开(公告)号：US09461653B2

公开(公告)日：2016-10-04

申请号：US14985985

申请日：2015-12-31

Applicant: Silicon Laboratories Inc.

Inventor： Michael H. Perrott

IPC: H03L7/06 ,  H03L7/08 ,  H03L7/093 ,  H03M1/08 ,  H03M1/66 ,  G04F10/00 ,  H03L7/099 ,  H03M3/00 ,  H03L7/085 ,  H02M3/07 ,  H03M7/30

CPC classification number: H03L7/0802 ,  G04F10/005 ,  H02M3/07 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0995 ,  H03M1/0836 ,  H03M1/0854 ,  H03M1/66 ,  H03M3/358 ,  H03M3/368 ,  H03M7/3004

Abstract: A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators.

Abstract translation: 锁相环（PLL）包括时间到电压转换器，以将参考信号和PLL的反馈信号之间的相位误差转换成一个或多个电压信号。 基于振荡器的模数转换器（ADC）接收一个或多个电压信号，并根据电压控制一个或多个振荡器。 基于振荡器的ADC基于一个或多个振荡器的频率来确定对应于相位误差的数字值。

公开(公告)号：US20160182081A1

公开(公告)日：2016-06-23

申请号：US14575167

申请日：2014-12-18

Applicant: Silicon Laboratories Inc.

Inventor： Michael H. Perrott ,  Louis Nervegna

IPC: H03M3/00

CPC classification number: H03M3/362 ,  G01D5/24 ,  G01N27/26 ,  G01R17/105 ,  G01R27/2605 ,  H03M3/464 ,  H03M3/476 ,  H03M3/496 ,  Y10T307/729

Abstract: A capacitance-to-digital converter circuit s a capacitor bridge circuit to sense a difference in capacitance between sense capacitors and fixed capacitors in the bridge circuit. The sense capacitors vary according to a sensed parameter. Auxiliary capacitor digital to analog converters (DACs) are coupled to the capacitor bridge circuit to cancel the sensed difference. An analog to digital converter (ADC) receives a signal generated by the capacitor bridge circuit and the auxiliary capacitor DACs and converts the received signal to a digital signal. A digital accumulator accumulates the ADC output, whose output represents the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output is used to control the auxiliary capacitor DACs to offset the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output also provides the basis for the capacitance-to-digital circuit output.

Abstract translation: 电容 - 数字转换器电路是用于感测桥式电路中的感测电容器和固定电容器之间的电容差的电容器桥接电路。 感测电容器根据感测参数而变化。 辅助电容器数模转换器（DAC）耦合到电容器桥接电路以消除感测到的差异。 模数转换器（ADC）接收由电容器桥电路和辅助电容DAC产生的信号，并将接收的信号转换为数字信号。 数字累加器累加ADC输出，其输出表示感测电容器和固定电容器之间的电容差。 累加器输出用于控制辅助电容DAC以抵消感测电容器和固定电容器之间的电容差。 累加器输出也为电容 - 数字电路输出提供了基础。

公开(公告)号：US09246500B2

公开(公告)日：2016-01-26

申请号：US14448466

申请日：2014-07-31

Applicant: Silicon Laboratories Inc.

Inventor： Michael H. Perrott

IPC: H03L7/06 ,  H03L7/093 ,  H03L7/08 ,  H03M1/08 ,  H03M1/66 ,  G04F10/00 ,  H03L7/099 ,  H03M3/00 ,  H03L7/085 ,  H02M3/07

CPC classification number: H03L7/0802 ,  G04F10/005 ,  H02M3/07 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0995 ,  H03M1/0836 ,  H03M1/0854 ,  H03M1/66 ,  H03M3/358 ,  H03M3/368 ,  H03M7/3004

Abstract: Quantization noise in a fractional-N phase-locked loop (PLL) is canceled using a capacitor-based digital to analog converter (DAC). A phase error is detected between a reference signal and a feedback signal in the PLL. A charge pump circuit charges a first capacitor circuit based on the phase error to generate a phase error voltage corresponding to the phase error. The capacitor based DAC generates a quantization error correction voltage based on a digital value corresponding to the quantization error, which is then combined with the phase error voltage to cancel the quantization error.

Abstract translation: 使用基于电容的数/模转换器（DAC）来消除分数N锁相环（PLL）中的量化噪声。 在PLL中的参考信号和反馈信号之间检测到相位误差。 电荷泵电路基于相位误差对第一电容器电路充电，以产生与相位误差相对应的相位误差电压。 基于电容器的DAC基于与量化误差对应的数字值产生量化误差校正电压，然后将其与相位误差电压组合以消除量化误差。

公开(公告)号：US20150145571A1

公开(公告)日：2015-05-28

申请号：US14448447

申请日：2014-07-31

Applicant: Silicon Laboratories Inc.

Inventor： Michael H. Perrott

IPC: H03L7/093 ,  H03L7/085

CPC classification number: H03L7/0802 ,  G04F10/005 ,  H02M3/07 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0995 ,  H03M1/0836 ,  H03M1/0854 ,  H03M1/66 ,  H03M3/358 ,  H03M3/368 ,  H03M7/3004

Abstract: A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.

Abstract translation: 分数N锁相环（PLL）包括非线性时间到数字转换器，其产生对应于分数N PLL的反馈信号与参考信号之间的时间差的相位误差的数字表示。 非线性量化噪声消除电路提供校正信号以确保生成的数字表示具有降低的量化噪声。 校正信号可以应用于模拟或数字域。

公开(公告)号：US20150145566A1

公开(公告)日：2015-05-28

申请号：US14554798

申请日：2014-11-26

Applicant: Silicon Laboratories Inc.

Inventor： Michael H. Perrott

IPC: H03L7/099 ,  H03L7/093 ,  H03L7/08

CPC classification number: H03L7/0991 ,  H03L7/0802 ,  H03L7/093 ,  H03L7/0994

Abstract: A hybrid analog/digital control approach for a digitally controlled oscillator augments a digital control path with an analog control path that acts to center the digital control path control signal within its range. The digital control path controls a first group of varactors within an oscillator tank circuit using a digital filter and a delta sigma modulator, which generates a dithered control signal for at least one of the first group of varactors. The analog control path controls a second group of varactors in the tank circuit but actively tunes only one varactor at a time. The analog control path performs relatively low bandwidth centering of the digital control signal resulting in negligible impact on PLL bandwidth, stability, and noise performance. Instead, the digital control path dominates in setting the PLL dynamic and noise behavior, and has reduced range requirements due to the centering action.

Abstract translation: 用于数字控制振荡器的混合模拟/数字控制方法通过模拟控制路径增加数字控制路径，该模拟控制路径用于将数字控制路径控制信号置于其范围内。 数字控制路径使用数字滤波器和Δ-Σ调制器来控制振荡器振荡电路内的第一组变容二极管，其产生用于第一组变容二极管中的至少一个的抖动控制信号。 模拟控制路径控制油箱回路中的第二组变容二极管，但一次仅主动调谐一个变容二极管。 模拟控制路径执行数字控制信号的相对低带宽居中，从而对PLL带宽，稳定性和噪声性能造成可忽略的影响。 相反，数字控制路径在设置PLL动态和噪声行为方面占主导地位，并且由于定心动作而降低了范围要求。