公开(公告)号：US20190087343A1

公开(公告)日：2019-03-21

申请号：US16193156

申请日：2018-11-16

Applicant: Silicon Motion, Inc.

Inventor： Yang-Chih Shen ,  Che-Wei Hsu

IPC: G06F12/0873

Abstract: The invention introduces a method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the following steps. A write command for programming at least a data page into a first address is received from a master device via an access interface. It is determined whether a block of data to be programmed has been collected, where the block contains a specified number of pages. The data page is stored in a DRAM (Dynamic Random Access Memory) and cache information is updated to indicate that the data page has not been programmed into the storage unit, and to also indicate the location of the DRAM caching the data page when the block of data to be programmed has not been collected.

公开(公告)号：US20190087326A1

公开(公告)日：2019-03-21

申请号：US16197034

申请日：2018-11-20

Applicant: Silicon Motion, Inc.

Inventor： Ting-Hsing Wang ,  Yang-Chih Shen

IPC: G06F12/02

Abstract: A data storage device with a non-volatile memory on which a garbage collection operation is segmented to be accomplished at separate time intervals. Host commands are inserted to be executed between the separate time intervals. A data swap stage or/and an F2H table update stage or/and an H2F table update stage for a garbage collection operation may be segmented to be performed at separate time intervals.

公开(公告)号：US20180239670A1

公开(公告)日：2018-08-23

申请号：US15948586

申请日：2018-04-09

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/02

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, is disclosed to include at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.

公开(公告)号：US20170308318A1

公开(公告)日：2017-10-26

申请号：US15643501

申请日：2017-07-07

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F3/06 ,  G06F12/02 ,  G11C11/56

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US09785546B2

公开(公告)日：2017-10-10

申请号：US14738481

申请日：2015-06-12

Applicant: Silicon Motion, Inc.

Inventor： Yang-Chih Shen

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/7201

Abstract: A method for scheduling read commands, performed by a processing unit, including at least the following steps. Logical read commands are received from a master device via a first access interface, where each logical read command requests to read data of a logical address. First physical storage locations of mapping segments associated with the logical addresses are obtained from a high-level mapping table, and a second access interface is directed to read the mapping segments from the first physical storage locations of a storage unit. Second physical storage locations associated with the logical addresses are obtained from the mapping segments, and the second access interface is directed to read data from the second physical storage locations of the storage unit. The first access interface is directed to clock the data of the logical addresses out to the master device.

公开(公告)号：US09741451B2

公开(公告)日：2017-08-22

申请号：US14711472

申请日：2015-05-13

Applicant: Silicon Motion, Inc.

Inventor： Ching-Ke Chen ,  Po-Sheng Chou ,  Yang-Chih Shen

IPC: G06F13/00 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/108 ,  G11C2029/0411

Abstract: A data storage device including a flash memory and a controller. The flash memory includes a plurality of chips, each of the chips includes a plurality of pages, the pages are arranged to assemble into a super block, the pages of the super block are numbered 0˜X from top to bottom of the super block, the pages with number 0˜Y−1 constitute a data area, and the pages with numbers Y˜X constitute a RAID parity area. The controller corrects data of the data area according to data of the RAID parity area when the data in the data area cannot be successfully read.

公开(公告)号：US20160070653A1

公开(公告)日：2016-03-10

申请号：US14738481

申请日：2015-06-12

Applicant: Silicon Motion, Inc.

Inventor： Yang-Chih Shen

IPC: G06F12/10

CPC classification number: G06F12/0246 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/7201

Abstract: A method for scheduling read commands, performed by a processing unit, including at least the following steps. Logical read commands are received from a master device via a first access interface, where each logical read command requests to read data of a logical address. First physical storage locations of mapping segments associated with the logical addresses are obtained from a high-level mapping table, and a second access interface is directed to read the mapping segments from the first physical storage locations of a storage unit. Second physical storage locations associated with the logical addresses are obtained from the mapping segments, and the second access interface is directed to read data from the second physical storage locations of the storage unit. The first access interface is directed to clock the data of the logical addresses out to the master device.

Abstract translation: 一种用于调度由处理单元执行的读取命令的方法，至少包括以下步骤。 通过第一访问接口从主设备接收逻辑读命令，其中每个逻辑读命令请求读取逻辑地址的数据。 从高级映射表获得与逻辑地址相关联的映射段的第一物理存储位置，并且第二访问接口用于从存储单元的第一物理存储位置读取映射段。 从映射段获得与逻辑地址相关联的第二物理存储位置，并且第二访问接口用于从存储单元的第二物理存储位置读取数据。 第一个访问接口用于将逻辑地址的数据提供给主设备。

公开(公告)号：US20150058537A1

公开(公告)日：2015-02-26

申请号：US14330853

申请日：2014-07-14

Applicant: Silicon Motion, Inc.

Inventor： Yang-Chih Shen

IPC: G06F12/02 ,  G06F11/10 ,  G11C14/00

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0685 ,  G06F11/10 ,  G06F11/1012 ,  G06F11/1072 ,  G06F11/1076 ,  G06F11/108 ,  G06F13/16 ,  G06F13/28 ,  G06F2212/7208 ,  G11C11/5628 ,  G11C14/0018 ,  G11C16/3427 ,  G11C2029/0411

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A storage-unit access interface is directed to program data into the nth wordline of a storage unit. The storage-unit access interface is directed to program the same data into the (n−1)th wordline of the storage unit after the storage unit completes the data programming of the nth wordline of the storage unit. The storage-unit access interface is directed to program the same data into the (n−2)th wordline of the storage unit after the storage unit completes the data programming of the (n−1)th wordline of the storage unit, where n is an integer greater than 2.

Abstract translation: 用于访问由处理单元执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 存储单元访问接口被引导到存储单元的第n个字线中的程序数据。 在存储单元完成存储单元的第n个字线的数据编程之后，存储单元访问接口用于将相同的数据编程到存储单元的第（n-1）个字线中。 在存储单元完成存储单元的第（n-1）个字线的数据编程之后，存储单元访问接口用于将相同的数据编程到存储单元的第（n-2）个字线中，其中n 是大于2的整数。

公开(公告)号：US20130107625A1

公开(公告)日：2013-05-02

申请号：US13658086

申请日：2012-10-23

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Ching-Hui Lin ,  Yang-Chih Shen ,  Chun-Chieh Kuo

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641

Abstract: The invention provides a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a flash memory and a flash memory controller. The flash memory comprises a write circuit and a memory cell array comprising a plurality of memory cells, wherein the write circuit is coupled to the memory cell array to write data in the memory cells. The flash memory controller is coupled to the write circuit, obtains a total capacity and a used data amount of the flash memory, and directs the write circuit to perform data writing in a one-bit mode when a ratio of the user data amount to the total capacity is less than a first predetermined value.

Abstract translation: 本发明提供一种闪存装置。 在一个实施例中，闪存装置包括闪速存储器和闪存控制器。 闪速存储器包括写电路和包括多个存储单元的存储单元阵列，其中写电路耦合到存储单元阵列以将数据写入存储单元。 闪速存储器控制器耦合到写入电路，获得闪存的总容量和使用的数据量，并且当用户数据量与存储器的比率相对应时，引导写入电路以一位模式执行数据写入 总容量小于第一预定值。

公开(公告)号：US11126558B2

公开(公告)日：2021-09-21

申请号：US16728294

申请日：2019-12-27

Applicant: Silicon Motion, Inc.

Inventor： Wei-Lin Kao ,  Yang-Chih Shen ,  Jian-Yu Chen

IPC: G06F12/08 ,  G06F12/0882 ,  G06F12/0873 ,  G06F9/54 ,  G06F13/16 ,  G06F12/02

Abstract: A high-performance data storage device is disclosed. A controller updates a sub mapping table on the temporary storage in response to a write command of the non-volatile memory issued by a host. The mapping sub-table corresponds to a logical group involved in the write command and is downloaded from the non-volatile memory. When the mapping sub-table has not been completely downloaded to the temporary storage memory, the controller pushes the write command to a waiting queue to avoid dragging the performance of the data storage device.