公开(公告)号：US09502333B2

公开(公告)日：2016-11-22

申请号：US14056230

申请日：2013-10-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Meng-Tsung Lee ,  Yi-Che Lai ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/1401 ,  H01L2224/1412 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.

Abstract translation: 提供一种半导体器件，包括：具有相对的第一和第二表面的衬底和穿过第一和第二表面的多个导电通孔; 绝缘层，形成在所述基板的所述第一表面上，并暴露所述导电通孔的端部; 以及在导电通孔的端部的周边形成在绝缘层上的缓冲层，从而提高产品的可靠性和良好的产率。

公开(公告)号：US20160079110A1

公开(公告)日：2016-03-17

申请号：US14849639

申请日：2015-09-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kuan-Wei Chuang ,  Shih-Kuang Chiu ,  Chun-Tang Lin ,  Jung-Pang Huang

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528

CPC classification number: H01L21/6835 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/528 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/18162

Abstract: A semiconductor package is provided, which includes: a carrier; a frame having a plurality of openings, wherein the frame is bonded to the carrier and made of a material different from that of the carrier; a plurality of electronic elements disposed in the openings of the frame, respectively; an encapsulant formed in the openings of the frame for encapsulating the electronic elements; and a circuit layer formed on and electrically connected to the electronic elements. By accurately controlling the size of the openings of the frame, the present invention increases the accuracy of positioning of the electronic elements so as to improve the product yield in subsequent processes.

Abstract translation: 提供一种半导体封装，其包括：载体; 具有多个开口的框架，其中所述框架结合到所述载体并且由与所述载体的材料不同的材料制成; 分别设置在框架的开口中的多个电子元件; 形成在框架的开口中的密封剂，用于封装电子元件; 以及形成在电子元件上并电连接到电子元件的电路层。 通过精确地控制框架的开口的尺寸，本发明提高了电子元件的定位精度，从而提高后续处理中的产品产量。

公开(公告)号：US20150069628A1

公开(公告)日：2015-03-12

申请号：US14259629

申请日：2014-04-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Tsung Tseng ,  Yi-Che Lai ,  Shih-Kuang Chiu ,  Mao-Hua Yeh

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/11

Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

Abstract translation: 提供一种半导体封装，包括具有多个导电通孔的半导体衬底，形成在半导体衬底上的缓冲层，形成在导电通孔的端表面上并覆盖缓冲层的多个导电焊盘。 在回流过程中，缓冲层大大降低了热应力，从而消除了导电焊盘界面处的开裂现象。 还提供了一种制造这种半导体封装的方法。

公开(公告)号：US20140134797A1

公开(公告)日：2014-05-15

申请号：US14013512

申请日：2013-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Yuan Chi ,  Jung-Pang Huang ,  Yan-Heng Chen ,  Hsi-Chang Hsu ,  Chiang-Cheng Chang ,  Shih-Kuang Chiu

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips.

Abstract translation: 公开了一种制造半导体封装件的方法，其包括以下步骤：提供具有释放层和依次在其上形成的粘合剂层的载体; 在所述粘合剂层上设置多个半导体芯片; 在粘合剂层上形成密封剂以封装半导体芯片; 将衬底设置在密封剂上; 将释放层暴露于通过载体的光，以便去除释放层和载体; 然后去除粘合剂层，从而有效地防止半导体芯片暴露于光，以避免对半导体芯片的任何光损坏。

公开(公告)号：US10950507B2

公开(公告)日：2021-03-16

申请号：US15972837

申请日：2018-05-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Chi-Hsin Chiu ,  Shih-Kuang Chiu

IPC: G01R1/073 ,  H01L21/66 ,  H01L23/498 ,  H01L21/48

Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.

公开(公告)号：US20190122898A1

公开(公告)日：2019-04-25

申请号：US16225230

申请日：2018-12-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Hsin Chiu ,  Shih-Kuang Chiu

IPC: H01L21/52 ,  H01L23/538 ,  H01L21/78 ,  H01L23/00

Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.

公开(公告)号：US10199239B2

公开(公告)日：2019-02-05

申请号：US14823341

申请日：2015-08-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Hsin Chiu ,  Shih-Kuang Chiu

IPC: H01L21/52 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.

公开(公告)号：US20180254227A1

公开(公告)日：2018-09-06

申请号：US15972837

申请日：2018-05-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Chi-Hsin Chiu ,  Shih-Kuang Chiu

IPC: H01L21/66 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L22/14 ,  H01L21/486 ,  H01L22/20 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16

Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.

公开(公告)号：US10049955B2

公开(公告)日：2018-08-14

申请号：US15497964

申请日：2017-04-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L21/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/538

Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.

公开(公告)号：US09487393B2

公开(公告)日：2016-11-08

申请号：US14821010

申请日：2015-08-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Hsin-Yi Liao ,  Chun-An Huang ,  Shih-Kuang Chiu ,  Chien-An Chen

IPC: H01L29/00 ,  B81C1/00 ,  H01L29/84

CPC classification number: B81C1/00301 ,  B81B2201/0264 ,  B81C1/00269 ,  B81C2203/0154 ,  H01L29/84 ,  H01L2224/48091 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path.

Abstract translation: 提供了具有压力传感器及其制造方法的晶片级封装。 将具有压力传感器的晶片接合到盖上，并且在晶片上形成电连接焊盘。 在切割盖子之后，进行引线键合和封装处理。 接合线的端部暴露并用作电连接路径。 为了形成压力传感器路径，在晶片的底面上形成底部开口。