公开(公告)号：US20140332976A1

公开(公告)日：2014-11-13

申请号：US14013420

申请日：2013-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Yan-Yi Liao ,  Hung-Wen Liu ,  Chieh-Yuan Chi ,  Hsi-Chang Hsu

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/12042 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract translation: 公开了一种半导体封装，其包括：具有至少一个开口的载体; 形成在所述载体上和所述开口中的多个导电迹线; 设置在所述开口中并电连接到所述导电迹线的第一半导体元件; 设置在所述开口中的所述第一半导体元件上的第二半导体元件; 以及形成在载体上的再分布层结构和用于电连接导电迹线和第二半导体元件的第二半导体元件。 由于半导体元件被嵌入并因此定位在载体的开口中，所以本发明消除了在形成再分配层结构之前进行模制处理并防止半导体元件移位的需要。

公开(公告)号：US20190109092A1

公开(公告)日：2019-04-11

申请号：US16216621

申请日：2018-12-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Rui-Feng Tai ,  Hsiao-Chun Huang ,  Chun-Hung Lu ,  Hsi-Chang Hsu ,  Shih-Ching Chen

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/68 ,  H01L21/56

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit.

公开(公告)号：US08766456B2

公开(公告)日：2014-07-01

申请号：US13660223

申请日：2012-10-25

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsi-Chang Hsu ,  Hsin-Hung Chou ,  Hung-Wen Liu ,  Hsin-Yi Liao ,  Chiang-Cheng Chang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a semiconductor element on a carrier; forming an encapsulant on the carrier to encapsulant the semiconductor element; forming at least one through hole penetrating the encapsulant; forming a hollow conductive through hole in the through hole and, at the same time, forming a circuit layer on an active surface of the semiconductor element and the encapsulant; forming an insulating layer on the circuit layer; and removing the carrier. By forming the conductive through hole and the circuit layer simultaneously, the invention eliminates the need to form a dielectric layer before forming the circuit layer and dispenses with the conventional chemical mechanical polishing (CMP) process, thus greatly improving the fabrication efficiency.

Abstract translation: 提供一种制造半导体封装的方法，包括：将半导体元件设置在载体上; 在所述载体上形成密封剂以密封所述半导体元件; 形成穿透所述密封剂的至少一个通孔; 在通孔中形成中空的导电通孔，同时在半导体元件的有源表面和密封剂上形成电路层; 在电路层上形成绝缘层; 并移除载体。 通过同时形成导电通孔和电路层，本发明消除了在形成电路层之前形成电介质层并省去常规化学机械抛光（CMP）工艺的需要，从而大大提高了制造效率。

公开(公告)号：US20140134797A1

公开(公告)日：2014-05-15

申请号：US14013512

申请日：2013-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Yuan Chi ,  Jung-Pang Huang ,  Yan-Heng Chen ,  Hsi-Chang Hsu ,  Chiang-Cheng Chang ,  Shih-Kuang Chiu

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips.

Abstract translation: 公开了一种制造半导体封装件的方法，其包括以下步骤：提供具有释放层和依次在其上形成的粘合剂层的载体; 在所述粘合剂层上设置多个半导体芯片; 在粘合剂层上形成密封剂以封装半导体芯片; 将衬底设置在密封剂上; 将释放层暴露于通过载体的光，以便去除释放层和载体; 然后去除粘合剂层，从而有效地防止半导体芯片暴露于光，以避免对半导体芯片的任何光损坏。

公开(公告)号：US11610850B2

公开(公告)日：2023-03-21

申请号：US17160749

申请日：2021-01-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chih-Hsun Hsu ,  Chi-Jen Chen ,  Hsi-Chang Hsu ,  Yuan-Hung Hsu ,  Rui-Feng Tai ,  Don-Son Jiang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.

公开(公告)号：US10903167B2

公开(公告)日：2021-01-26

申请号：US16285813

申请日：2019-02-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jun-Chang Ding ,  Hong-Da Chang ,  Hsi-Chang Hsu

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/498 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31

Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.

公开(公告)号：US09397081B2

公开(公告)日：2016-07-19

申请号：US14873445

申请日：2015-10-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Yan-Yi Liao ,  Hung-Wen Liu ,  Chieh-Yuan Chi ,  Hsi-Chang Hsu

IPC: H01L23/31 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/12042 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract translation: 公开了一种半导体封装，其包括：具有至少一个开口的载体; 形成在所述载体上和所述开口中的多个导电迹线; 设置在所述开口中并电连接到所述导电迹线的第一半导体元件; 设置在所述开口中的所述第一半导体元件上的第二半导体元件; 以及形成在载体上的再分布层结构和用于电连接导电迹线和第二半导体元件的第二半导体元件。 由于半导体元件被嵌入并因此定位在载体的开口中，所以本发明消除了在形成再分配层结构之前进行模制处理并防止半导体元件移位的需要。

公开(公告)号：US09177859B2

公开(公告)日：2015-11-03

申请号：US14013420

申请日：2013-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Yan-Yi Liao ,  Hung-Wen Liu ,  Chieh-Yuan Chi ,  Hsi-Chang Hsu

IPC: H01L23/31 ,  H01L23/13 ,  H01L23/538 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/12042 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract translation: 公开了一种半导体封装，其包括：具有至少一个开口的载体; 形成在所述载体上和所述开口中的多个导电迹线; 设置在所述开口中并电连接到所述导电迹线的第一半导体元件; 设置在所述开口中的所述第一半导体元件上的第二半导体元件; 以及形成在载体上的再分布层结构和用于电连接导电迹线和第二半导体元件的第二半导体元件。 由于半导体元件被嵌入并因此定位在载体的开口中，所以本发明消除了在形成再分配层结构之前进行模制处理并防止半导体元件移位的需要。

公开(公告)号：US12107055B2

公开(公告)日：2024-10-01

申请号：US18109120

申请日：2023-02-13

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chih-Hsun Hsu ,  Chi-Jen Chen ,  Hsi-Chang Hsu ,  Yuan-Hung Hsu ,  Rui-Feng Tai ,  Don-Son Jiang

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3157 ,  H01L24/05 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/05556 ,  H01L2224/16227

Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.

公开(公告)号：US11532528B2

公开(公告)日：2022-12-20

申请号：US17160720

申请日：2021-01-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chi-Jen Chen ,  Hsi-Chang Hsu ,  Yuan-Hung Hsu ,  Chang-Fu Lin ,  Don-Son Jiang

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.