公开(公告)号：US09520304B2

公开(公告)日：2016-12-13

申请号：US14074148

申请日：2013-11-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Shih-Kuang Chiu

IPC: H01L23/28 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：提供具有载体的半导体结构，形成在载体上的电路部分和设置在电路部分上的多个半导体元件; 在所述半导体元件上设置层压部件; 在用于封装半导体元件的电路部分上形成绝缘层; 并移除载体。 层叠构件增加相邻半导体元件之间的强度，以克服当移除载体时由半导体元件和绝缘层之间的CTE失配引起的常规裂纹问题。

公开(公告)号：US20200350285A1

公开(公告)日：2020-11-05

申请号：US16554779

申请日：2019-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Ching Ho ,  Bo-Hao Ma ,  Yu-Ting Xue ,  Ching-Hung Tseng ,  Guan-Hua Lu ,  Hong-Da Chang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

公开(公告)号：US20190214372A1

公开(公告)日：2019-07-11

申请号：US16356589

申请日：2019-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Yih-Jenn Jiang

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/552 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/683 ,  H01L21/56 ,  H01L25/00

Abstract: An electronic package is provided, including: a first circuit structure; an electronic component and a conductive pillar disposed on the first circuit structure; an encapsulation layer encapsulating the electronic component and the conductive pillar; a second circuit structure disposed on the encapsulation layer; and a shielding layer encapsulating the first circuit structure, a side surface of the encapsulation layer, and a side surface of the second circuit structure. The electronic component is surrounded by the shielding layer, and is protected from electromagnetic interference. A method for fabricating the electronic package is also provided.

公开(公告)号：US09425119B2

公开(公告)日：2016-08-23

申请号：US14273952

申请日：2014-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Shih-Kuang Chiu

IPC: H01L23/28 ,  H01L21/768 ,  B81B7/00 ,  G01L19/00 ,  G01L19/14 ,  H01L23/10

CPC classification number: H01L23/28 ,  B81B7/0061 ,  B81B7/007 ,  B81B2207/098 ,  G01L19/0076 ,  G01L19/147 ,  H01L23/10 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts; a chip having a surface with a conductive layer and an opposite surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the wafer with the seal ring surrounding the thin film and the electrical contacts located outside the seal ring; an encapsulant formed on the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant with one ends exposed from a top surface of the encapsulant and the other ends in electrical connection with the electrical contacts; and a through hole penetrating the wafer and communicating with the concave portion, thereby reducing the fabrication cost and size of the package structure.

Abstract translation: 提供了一种封装结构，其包括：具有带有凹槽的表面的晶片，封闭凹槽的开口端的薄膜和电触头; 芯片，其表面具有导电层，与凹部相对的表面和位于凹部周边的密封环，芯片设置在晶片上，密封环围绕薄膜，电触点位于 密封环外; 形成在晶片上用于封装芯片和电触点的密封剂; 多个次级导电线嵌入密封剂中，其一端从密封剂的顶表面露出，另一端与电触点电连接; 以及穿透晶片并与凹部连通的通孔，从而降低了封装结构的制造成本和尺寸。

公开(公告)号：US20150325556A1

公开(公告)日：2015-11-12

申请号：US14487548

申请日：2014-09-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Hsien-Wen Chen ,  Hong-Da Chang ,  Mao-Hua Yeh

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L23/49 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15323 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.

Abstract translation: 提供一种封装结构，其包括：具有多个导电连接部分的芯片载体; 至少设置在所述芯片载体上的电子元件; 多个导线分别竖立设置在导电连接部分上; 形成在所述芯片载体上用于封装所述导线和所述电子元件的密封剂，其中所述导线的一端从所述密封剂露出; 以及形成在密封剂上并电连接到导线的露出端的电路层。 根据本发明，导线用作互连结构。 由于导线的线径小，导线之间的间距可以最小化，因此本发明可以减小芯片载体的尺寸并满足小型化要求。

公开(公告)号：US20150162264A1

公开(公告)日：2015-06-11

申请号：US14273952

申请日：2014-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  G01K13/00 ,  G01L1/00 ,  H01L21/768 ,  H01L23/28

CPC classification number: H01L23/28 ,  B81B7/0061 ,  B81B7/007 ,  B81B2207/098 ,  G01L19/0076 ,  G01L19/147 ,  H01L23/10 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts; a chip having a surface with a conductive layer and an opposite surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the wafer with the seal ring surrounding the thin film and the electrical contacts located outside the seal ring; an encapsulant formed on the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant with one ends exposed from a top surface of the encapsulant and the other ends in electrical connection with the electrical contacts; and a through hole penetrating the wafer and communicating with the concave portion, thereby reducing the fabrication cost and size of the package structure.

Abstract translation: 提供了一种封装结构，其包括：具有带有凹槽的表面的晶片，封闭凹槽的开口端的薄膜和电触头; 芯片，其表面具有导电层，与凹部相对的表面和位于凹部周边的密封环，芯片设置在晶片上，密封环围绕薄膜，电触点位于 密封环外; 形成在晶片上用于封装芯片和电触点的密封剂; 多个次级导电线嵌入密封剂中，其一端从密封剂的顶表面露出，另一端与电触点电连接; 以及穿透晶片并与凹部连通的通孔，从而降低了封装结构的制造成本和尺寸。

公开(公告)号：US10903167B2

公开(公告)日：2021-01-26

申请号：US16285813

申请日：2019-02-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jun-Chang Ding ,  Hong-Da Chang ,  Hsi-Chang Hsu

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/498 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31

Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.

公开(公告)号：US20200043908A1

公开(公告)日：2020-02-06

申请号：US16164416

申请日：2018-10-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chee-Key Chung ,  Chang-Fu Lin ,  Han-Hung Chen ,  Jen-Chieh Hsiao ,  Rung-Jeng Lin ,  Kuo-Hua Yu ,  Hong-Da Chang

IPC: H01L25/00 ,  H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00

Abstract: A package stacked structure and a method for fabricating the same are provided. The method includes providing a wiring structure disposed with a carrier and a carrier structure provided with an electronic component. The wiring structure is bonded to the carrier structure via a plurality of conductive elements. An encapsulating layer is formed between the wiring structure and the carrier structure and encapsulates the conductive elements and the electronic component. The carrier is then removed. With the arrangement of the carrier, the structural strength of the wiring structure is improved, and warpage of the wiring structure is prevented before stacking the wiring structure onto the carrier structure.

公开(公告)号：US09487393B2

公开(公告)日：2016-11-08

申请号：US14821010

申请日：2015-08-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Hsin-Yi Liao ,  Chun-An Huang ,  Shih-Kuang Chiu ,  Chien-An Chen

IPC: H01L29/00 ,  B81C1/00 ,  H01L29/84

CPC classification number: B81C1/00301 ,  B81B2201/0264 ,  B81C1/00269 ,  B81C2203/0154 ,  H01L29/84 ,  H01L2224/48091 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path.

Abstract translation: 提供了具有压力传感器及其制造方法的晶片级封装。 将具有压力传感器的晶片接合到盖上，并且在晶片上形成电连接焊盘。 在切割盖子之后，进行引线键合和封装处理。 接合线的端部暴露并用作电连接路径。 为了形成压力传感器路径，在晶片的底面上形成底部开口。

公开(公告)号：US11676877B2

公开(公告)日：2023-06-13

申请号：US17747900

申请日：2022-05-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Chun-Chang Ting ,  Chi-Jen Chen

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/3178 ,  H01L21/563

Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.