公开(公告)号：US20210175196A1

公开(公告)日：2021-06-10

申请号：US16821095

申请日：2020-03-17

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Hsin-Yi Liao ,  Cheng-Kai Chang ,  Bo-Hao Ma ,  Chun-Chi Ke

IPC: H01L23/00

Abstract: A method for fabricating an electronic package is provided. A plurality of packaging structures are provided, each of which having a carrier and at least one electronic component disposed on the carrier. The plurality of packaging structures are disposed on a supporting plate. An encapsulation layer is formed on the supporting plate and encapsulates the plurality of packaging structures. Even if there are various types of electronic packages of different specifications in the market, the molds that the encapsulation layer uses can still be developed for a supporting plate of a certain specification. Therefore, the fabrication cost of the electronic package is reduced.

公开(公告)号：US09117698B2

公开(公告)日：2015-08-25

申请号：US14449278

申请日：2014-08-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Jung-Pang Huang ,  Hsin-Yi Liao ,  Shih-Kuang Chiu ,  Guang-Hwa Ma

IPC: H01L21/56 ,  H01L23/48 ,  H01L21/02 ,  H01L21/50 ,  H01L29/84 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L23/538

CPC classification number: H01L24/11 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/033 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/48227 ,  H01L2224/81 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.

Abstract translation: 半导体封装包括：具有相反的第一和第二表面的电介质层; 嵌入在介电层中并具有多个电极焊盘的半导体芯片; 分别设置在半导体芯片的电极焊盘上的多个第一金属柱，使得第一金属柱的顶端从第一表面露出; 至少第二金属柱穿透介电层，使得第二金属柱的两个相对端分别从第一表面和第二表面露出; 第一电路层，形成在第一表面上，用于电连接第一和第二金属柱; 以及形成在所述第二表面上用于电连接所述第二金属柱的第二电路层。 该半导体封装省去了用于在模塑料中形成导电柱的常规激光烧蚀和电镀工艺，从而节省制造时间和成本。

公开(公告)号：US20140342507A1

公开(公告)日：2014-11-20

申请号：US14449278

申请日：2014-08-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Jung-Pang Huang ,  Hsin-Yi Liao ,  Shih-Kuang Chiu ,  Guang-Hwa Ma

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/033 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/48227 ,  H01L2224/81 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.

Abstract translation: 半导体封装包括：具有相反的第一和第二表面的电介质层; 嵌入在介电层中并具有多个电极焊盘的半导体芯片; 分别设置在半导体芯片的电极焊盘上的多个第一金属柱，使得第一金属柱的顶端从第一表面露出; 至少第二金属柱穿透介电层，使得第二金属柱的两个相对端分别从第一表面和第二表面露出; 第一电路层，形成在第一表面上，用于电连接第一和第二金属柱; 以及形成在所述第二表面上用于电连接所述第二金属柱的第二电路层。 该半导体封装省去了用于在模塑料中形成导电柱的常规激光烧蚀和电镀工艺，从而节省制造时间和成本。

公开(公告)号：US09254994B2

公开(公告)日：2016-02-09

申请号：US14487602

申请日：2014-09-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Hsin Chiu ,  Chih-Ming Huang ,  Chang-Yueh Chan ,  Hsin-Yi Liao ,  Chun-Chi Ke

IPC: H01L29/24 ,  B81B7/00 ,  H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L23/00

CPC classification number: B81B7/0064 ,  B81B7/007 ,  B81B2207/095 ,  H01L21/56 ,  H01L23/315 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.

Abstract translation: 提供具有至少MEMS元件的封装结构，其包括具有电连接焊盘和MEMS元件的芯片; 设置在所述芯片上以覆盖所述MEMS元件并且具有设置在其上的金属层的盖; 电连接到电连接焊盘的第一子接合线; 电连接到金属层的第二子接合线; 设置在所述芯片上的密封剂，其中所述第一和第二子接合线的顶端从所述密封剂露出; 以及设置在密封剂上并电连接到第一子接合线的金属迹线。 封装结构有利地具有减小的尺寸，相对低的成本，不同的凸起位置和增强的EMI屏蔽效果。

公开(公告)号：US08878356B2

公开(公告)日：2014-11-04

申请号：US13660200

申请日：2012-10-25

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Cheng-Hsiang Liu ,  Kuang-Wei Huang ,  Chun-Hung Lin ,  Hsin-Yi Liao

IPC: H01L23/48 ,  H01L23/22 ,  H01L23/24 ,  H01L23/051 ,  H01L23/053 ,  H01L23/043

CPC classification number: H01L23/051 ,  B81B7/0064 ,  B81B2207/092 ,  B81C2203/0154 ,  H01L23/043 ,  H01L23/053 ,  H01L24/48 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A package structure is provided, including: a substrate having a ground pad and an MEMS element; a lid disposed on the substrate for covering the MEMS element; a wire segment electrically connected to the ground pad; an encapsulant encapsulating the lid and the wire segment; and a circuit layer formed on the encapsulant and electrically connected to the wire segment and the lid so as to commonly ground the substrate and the lid, thereby releasing accumulated electric charges on the lid so as to improve the reliability of the MEMS system and reduce the number of I/O connections.

Abstract translation: 提供一种封装结构，包括：具有接地焊盘和MEMS元件的衬底; 设置在所述基板上用于覆盖所述MEMS元件的盖; 电连接到接地垫的线段; 封装盖和线段的密封剂; 以及形成在密封剂上并电连接到线段和盖子上的电路层，以便共同接地衬底和盖子，从而释放盖上的积累的电荷，从而提高MEMS系统的可靠性并减少 I / O连接数。

公开(公告)号：US11195812B2

公开(公告)日：2021-12-07

申请号：US16821095

申请日：2020-03-17

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Hsin-Yi Liao ,  Cheng-Kai Chang ,  Bo-Hao Ma ,  Chun-Chi Ke

IPC: H01L23/00

Abstract: A method for fabricating an electronic package is provided. A plurality of packaging structures are provided, each of which having a carrier and at least one electronic component disposed on the carrier. The plurality of packaging structures are disposed on a supporting plate. An encapsulation layer is formed on the supporting plate and encapsulates the plurality of packaging structures. Even if there are various types of electronic packages of different specifications in the market, the molds that the encapsulation layer uses can still be developed for a supporting plate of a certain specification. Therefore, the fabrication cost of the electronic package is reduced.

公开(公告)号：US09487393B2

公开(公告)日：2016-11-08

申请号：US14821010

申请日：2015-08-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Hsin-Yi Liao ,  Chun-An Huang ,  Shih-Kuang Chiu ,  Chien-An Chen

IPC: H01L29/00 ,  B81C1/00 ,  H01L29/84

CPC classification number: B81C1/00301 ,  B81B2201/0264 ,  B81C1/00269 ,  B81C2203/0154 ,  H01L29/84 ,  H01L2224/48091 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path.

Abstract translation: 提供了具有压力传感器及其制造方法的晶片级封装。 将具有压力传感器的晶片接合到盖上，并且在晶片上形成电连接焊盘。 在切割盖子之后，进行引线键合和封装处理。 接合线的端部暴露并用作电连接路径。 为了形成压力传感器路径，在晶片的底面上形成底部开口。

公开(公告)号：US20140080242A1

公开(公告)日：2014-03-20

申请号：US14078845

申请日：2013-11-13

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-An Huang ,  Hsin-Yi Liao ,  Shih-Kuang Chiu

IPC: B81C1/00

CPC classification number: H01L29/84 ,  B81B7/007 ,  B81B2207/096 ,  B81C1/00301 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high.

Abstract translation: 封装结构包括具有多个电触头的微机电元件; 封装层，其包围微机电元件和电触点，微机电元件的底表面从封装层的下表面露出; 嵌入在所述封装层中的多个接合线，每个所述接合线的一端连接到所述电接触中的一个，另一端从所述封装层的下表面露出; 以及设置在所述封装层的下表面上的堆积层结构，所述堆积层包括至少一个电介质层和形成在所述电介质层中并且电连接到所述接合线的一端的多个导电盲孔 。 封装结构更容易精确地控制外部电触头的位置，并且制造程序的兼容性高。

公开(公告)号：US11114412B2

公开(公告)日：2021-09-07

申请号：US16686995

申请日：2019-11-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsin-Yi Liao ,  Cheng-Kai Chang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56 ,  H01L25/16 ,  H01L23/498

Abstract: An electronic package is provided, including: a first carrying structure having a first circuit layer; a package module disposed on the first carrying structure and electrically connected to the first circuit layer; a first electronic component disposed on the first carrying structure and electrically connected to the first circuit layer; and a second electronic component stacked on and electrically connected to the first electronic component. As the second electronic component is stacked with the first electronic component, a surface area of the first carrying structure that the first and second electronic components occupy is reduced, and the electronic package can have sufficient space to accommodate the package modules. A method for fabricating an electronic package is also provided.

公开(公告)号：US20210104491A1

公开(公告)日：2021-04-08

申请号：US16686995

申请日：2019-11-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsin-Yi Liao ,  Cheng-Kai Chang

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56 ,  H01L25/16

Abstract: An electronic package is provided, including: a first carrying structure having a first circuit layer; a package module disposed on the first carrying structure and electrically connected to the first circuit layer; a first electronic component disposed on the first carrying structure and electrically connected to the first circuit layer; and a second electronic component stacked on and electrically connected to the first electronic component. As the second electronic component is stacked with the first electronic component, a surface area of the first carrying structure that the first and second electronic components occupy is reduced, and the electronic package can have sufficient space to accommodate the package modules. A method for fabricating an electronic package is also provided.