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    SHORT CIRCUIT OF PROBES IN A CHAIN
    11.
    发明申请
    SHORT CIRCUIT OF PROBES IN A CHAIN 有权
    链中探针的短路

    公开(公告)号：US20130326147A1

    公开(公告)日：2013-12-05

    申请号：US13996012

    申请日：2011-12-29

    申请人： Simon C. Steely, JR. ,  Samantika Subramaniam ,  William C. Hasenplaugh ,  Joel S. Emer

    发明人： Simon C. Steely, JR. ,  Samantika Subramaniam ,  William C. Hasenplaugh ,  Joel S. Emer

    IPC分类号： G06F12/08

    CPC分类号： G06F12/084 ,  G06F12/082

    摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining that a local last accessor of the memory address may have a copy of the requested data up to date with the memory. The local last accessor may be within a local domain that the requester belongs to. The method may further comprise sending a cache probe to the local last accessor and retrieving a latest value of the requested data from the local last accessor to the requester.

    摘要翻译： 多核处理装置可以提供高速缓存探针和数据检索方法。 该方法可以包括将请求者的存储器请求发送到记录保存结构。 存储器请求可以具有存储请求的数据的存储器的存储器地址。 该方法还可以包括确定存储器地址的本地最后访问器可以具有与存储器一起的所请求数据的副本。 本地最后一个访问者可能在请求者所属的本地域内。 该方法还可以包括向本地最后一个访问器发送高速缓存探测器，并且从本地最后一个访问器检索所请求的数据的最新值到请求者。

    High bandwidth full-block write commands
    12.
    发明授权
    High bandwidth full-block write commands 有权

    公开(公告)号：US10102124B2

    公开(公告)日：2018-10-16

    申请号：US13993716

    申请日：2011-12-28

    申请人： Simon C. Steely, Jr. ,  William C. Hasenplaugh ,  Joel S. Emer ,  Samantika Subramaniam

    发明人： Simon C. Steely, Jr. ,  William C. Hasenplaugh ,  Joel S. Emer ,  Samantika Subramaniam

    IPC分类号： G06F13/00 ,  G06F12/0808 ,  G06F13/28

    摘要： A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high bandwidth write command. The method may comprise sending a write request from a requester to a record keeping structure. The write request may have a memory address of a memory that stores requested data. The method may further determine copies of the requested data being present in a distributed cache system outside the memory, sending invalidation requests to elements holding copies of the requested data in the distributed cache system, sending a notification to the requester to inform presence of copies of the requested data and sending a write response message after a latest value of the requested data and all invalidation acknowledgements have been received.

    Method and apparatus for optimizing the usage of cache memories
    13.
    发明授权
    Method and apparatus for optimizing the usage of cache memories 有权
    用于优化高速缓存存储器的使用的方法和装置

    公开(公告)号：US09418016B2

    公开(公告)日：2016-08-16

    申请号：US12974907

    申请日：2010-12-21

    申请人： Simon C. Steely, Jr. ,  Joel S. Emer ,  William C. Hasenplaugh

    发明人： Simon C. Steely, Jr. ,  Joel S. Emer ,  William C. Hasenplaugh

    IPC分类号： G06F12/02 ,  G06F12/08

    CPC分类号： G06F12/0891 ,  G06F12/0804 ,  G06F12/0815 ,  G06F2212/1028 ,  Y02D10/13

    摘要： A method and apparatus to reduce unnecessary write backs of cached data to a main memory and to optimize the usage of a cache memory tag directory. In one embodiment of the invention, the power consumption of a processor can be saved by eliminating write backs of cache memory lines that has information that has reached its end-of-life. In one embodiment of the invention, when a processing unit is required to clear one or more cache memory lines, it uses a write-zero command to clear the one or more cache memory lines. The processing unit does not perform a write operation to move or pass data values of zero to the one or more cache memory lines. By doing so, it reduces the power consumption of the processing unit.

    摘要翻译： 一种减少对主存储器的缓存数据的不必要的回写并优化高速缓存存储器标签目录的使用的方法和装置。 在本发明的一个实施例中，通过消除具有已经达到其使用寿命的信息的高速缓冲存储器线的写回，可以节省处理器的功耗。 在本发明的一个实施例中，当需要处理单元来清除一个或多个高速缓存存储器线时，它使用写入零命令来清除一个或多个高速缓存存储器线。 处理单元不执行写入操作以将数据值0移动或传递给一个或多个高速缓存存储器线。 通过这样做，它降低了处理单元的功耗。

    DOMAIN STATE
    14.
    发明申请
    DOMAIN STATE 有权
    域名

    公开(公告)号：US20140052920A1

    公开(公告)日：2014-02-20

    申请号：US13995991

    申请日：2011-12-29

    申请人： Simon C. Steely, JR. ,  William C. Hasenplaugh ,  Joel S. Emer

    发明人： Simon C. Steely, JR. ,  William C. Hasenplaugh ,  Joel S. Emer

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0802 ,  G06F12/0811 ,  G06F12/0817 ,  G06F13/00

    摘要： Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A value may be assigned to a domain state field of a tag entry in a cache tag directory. The cache tag directory may belong to a hierarchy of cache tag directories.Each tag entry may be associated with a cache line from a cache belonging to a first domain. The first domain may contain multiple caches. The value of the domain state field may indicate whether its associated cache line can be read or changed.

    摘要翻译： 通过读/写与缓存标签目录中的标签条目相关联的域状态字段来有效地维持高速缓存一致性的方法和装置。 可以将值分配给缓存标签目录中的标签条目的域状态字段。 缓存标签目录可能属于高速缓存标签目录的层次结构。 每个标签条目可以与来自属于第一域的高速缓存行相关联。 第一个域可能包含多个缓存。 域状态字段的值可以指示其相关联的高速缓存行是否可以被读取或改变。

    Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted
    15.
    发明授权
    Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted 失效
    多指针指令缓存，具有基于指令的探针提示生成和训练，从而预测缓存库或接下来要访问的方式

    公开(公告)号：US5933860A

    公开(公告)日：1999-08-03

    申请号：US902487

    申请日：1997-07-29

    申请人： Joel S. Emer ,  Simon Steely ,  Edward J. McLellan

    发明人： Joel S. Emer ,  Simon Steely ,  Edward J. McLellan

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/34 ,  G06F12/06

    CPC分类号： G06F9/3806 ,  G06F12/0862 ,  G06F9/3824 ,  G06F9/3832 ,  G06F2212/6082

    摘要： A computer system including an instruction cache (I-cache) having a plurality of banks for storing a subset of data from memory is shown to include a prediction mechanism for predicting which bank of the I-cache contains the required data. A prediction value, including a sequential prediction hint and a branch prediction hint, is associated with each instruction stored in the I-cache. The prediction value may either be stored with the I-cache data, or in a separate memory included before the I-cache. If the predicted value is incorrect, the predicted hint is `trained` to provide a higher degree of accuracy for repetitive instruction stream operation. Processor performance is additionally improved by providing a branch hint that allows for smoother transition between changing instruction streams.

    摘要翻译： 包括具有用于存储来自存储器的数据子集的多个存储体的指令高速缓存（I缓存）的计算机系统被示为包括用于预测I缓存的哪个存储体包含所需数据的预测机制。 包括顺序预测提示和分支预测提示的预测值与存储在I缓存中的每个指令相关联。 可以将预测值与I缓存数据一起存储，或者存储在I缓存之前的单独的存储器中。 如果预测值不正确，则预测提示被“训练”，以为重复的指令流操作提供更高的准确度。 通过提供一个分支提示，可以更改处理器性能，从而在更改指令流之间实现更平滑的转换。

    Integrated circuit chip having primary and secondary random access memories for a hierarchical cache
    18.
    发明授权
    Integrated circuit chip having primary and secondary random access memories for a hierarchical cache 失效
    集成电路芯片，具有用于分级高速缓存的主和次级随机存取存储器

    公开(公告)号：US5285323A

    公开(公告)日：1994-02-08

    申请号：US61273

    申请日：1993-05-13

    申请人： Ricky C. Hetherington ,  Francis X. McKeen ,  Joseph D. Marci ,  Tryggve Fossum ,  Joel S. Emer

    发明人： Ricky C. Hetherington ,  Francis X. McKeen ,  Joseph D. Marci ,  Tryggve Fossum ,  Joel S. Emer

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0897 ,  Y02B60/1225

    摘要： A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of data lines interconnecting the primary and secondary cache memories, the hierarchical cache memory is integrated on a plurality of integrated circuits which include all of the interconnecting data lines. Each integrated circuit includes a primary memory and a secondary memory for storing and retrieving data transferred over a first data input line and a first data output line that link the primary memory to a central processing unit. At any given time, a multi-bit word is addressed in the secondary memory, and a corresponding multi-bit word is addressed in the primary memory. The primary and secondary memories are interconnected by a first multi-line bus for transferring a multi-bit word read from the secondary memory to the primary memory, and by a second multi-line bus for transferring a multi-bit word read from the primary memory to the secondary memory. The secondary memory is linked to a main memory by a second data output line and a second data input line for sequential transmission of bits to exchange multi-bit words during a writeback and refill operation. In a preferred embodiment, data inputs of the primary memory and the secondary memory are wired in parallel to a serial-parallel shift register that is used as a common write buffer.

    摘要翻译： 分级缓存存储器包括高于主高速缓冲存储器的高速主缓存存储器和比主高速缓存存储器更大存储容量的较低速次级高速缓冲存储器。 为了管理互连主要和次要高速缓冲存储器的大量数据线，分层高速缓冲存储器集成在包括所有互连数据线的多个集成电路上。 每个集成电路包括主存储器和辅助存储器，用于存储和检索通过第一数据输入线传送的数据和将主存储器链接到中央处理单元的第一数据输出线。 在任何给定的时间，多位字在二级存储器中寻址，并且在主存储器中寻址相应的多位字。 主存储器和次存储器通过第一多行总线互连，用于将从副存储器读取的多位字传送到主存储器，以及用于传送从主存储器读取的多位字的第二多行总线 内存到二级内存。 次存储器通过第二数据输出线和第二数据输入线链接到主存储器，用于在写回和再填充操作期间顺序传输位以交换多位字。 在优选实施例中，主存储器和次存储器的数据输入与用作公共写入缓冲器的串行 - 并行移位寄存器并联布线。