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    HETEROSTRUCTURE AND METHOD OF FABRICATION
    12.
    发明申请
    HETEROSTRUCTURE AND METHOD OF FABRICATION 审中-公开

    公开(公告)号：US20200280298A1

    公开(公告)日：2020-09-03

    申请号：US16877309

    申请日：2020-05-18

    Applicant: Soitec

    Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

    IPC: H03H9/02 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H03H3/10

    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

    METHOD FOR PRODUCING COMPOSITE STRUCTURE WITH METAL/METAL BONDING
    13.
    发明申请
    METHOD FOR PRODUCING COMPOSITE STRUCTURE WITH METAL/METAL BONDING 有权
    用金属/金属结合生产复合结构的方法

    公开(公告)号：US20150179603A1

    公开(公告)日：2015-06-25

    申请号：US14411741

    申请日：2013-06-05

    Applicant: Soitec

    Inventor： Ionut Radu ,  Marcel Broekaart ,  Arnaud Castex ,  Gweltaz Gaudin ,  Gregory Riou

    IPC: H01L23/00 ,  H01L21/66 ,  H01L21/306

    CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L21/30604 ,  H01L21/30625 ,  H01L22/12 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/29124 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29176 ,  H01L2224/2918 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83895 ,  H01L2924/01014 ,  H01L2924/0504 ,  H01L2924/10253 ,  H01L2924/201 ,  Y10T428/12493 ,  Y10T428/12639 ,  Y10T428/12646 ,  Y10T428/12653 ,  Y10T428/12674

    Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa. The method further comprises, after the step of initiating the propagation of a bonding wave, a step of determining the level of stress induced during bonding of the two wafers, the level of stress being determined on the basis of a stress parameter Ct calculated using the formula Ct=Rc/Ep, where: Rc corresponds to the radius of curvature (in km) of the two-wafer assembly and Ep corresponds to the thickness (in μm) of the two-wafer assembly. The method further comprises a step of validating the bonding when the level of stress Ct determined is greater than or equal to 0.07.

    Abstract translation: 一种制造复合结构的方法，包括至少一个第一晶片与第二晶片的直接结合，并且包括启动键合波的传播的步骤，其中在所述第一和第二晶片传播之后的所述第一和第二晶片之间的结合界面 波具有小于或等于0.7J / m 2的结合能。 启动粘合波传播的步骤是在以下一个或多个条件下进行的：将晶片放置在小于20毫巴的压力的环境中和/或施加到两个晶片之一的机械压力 在0.1MPa和33.3MPa之间。 该方法还包括在开始粘合波的传播的步骤之后，确定在两个晶片的接合期间引起的应力水平的步骤，根据使用第二晶片计算出的应力参数Ct来确定应力水平 公式Ct = Rc / Ep，其中：Rc对应于两晶片组件的曲率半径（km），Ep对应于两晶片组件的厚度（μm）。 该方法还包括当确定的应力Ct大于或等于0.07时验证接合的步骤。

    Method for manufacturing a semiconductor-on-insulator substrate
    14.
    发明授权
    Method for manufacturing a semiconductor-on-insulator substrate 有权

    公开(公告)号：US12230533B2

    公开(公告)日：2025-02-18

    申请号：US17435017

    申请日：2020-03-26

    Applicant: Soitec

    Inventor： Marcel Broekaart ,  Arnaud Castex

    IPC: H01L21/762

    Abstract: A method for fabricating a semiconductor-on-insulator structure involves providing a donor substrate comprising a weakened zone delimiting a layer to be transferred, providing a receiver substrate, and bonding the donor substrate to the receiver substrate. The layer to be transferred is located on the bonding-interface side. A bonding wave is initiated at a first region on the periphery of the interface, and the wave is propagated toward a second region on the periphery of the interface opposite the first region. The difference in speed of propagation of the bonding wave between a central portion of the interface and a peripheral portion of the interface is controlled such that the speed of propagation of the bonding wave is lower in the central portion than in the peripheral portion. The donor substrate is detached along the weakened zone to transfer the layer to be transferred to the receiver substrate.

    Semiconductor-on-insulator substrate for rf applications
    17.
    发明授权
    Semiconductor-on-insulator substrate for rf applications 有权

    公开(公告)号：US11626319B2

    公开(公告)日：2023-04-11

    申请号：US17090608

    申请日：2020-11-05

    Applicant: Soitec

    Inventor： Arnaud Castex ,  Oleg Kononchuk

    IPC: H01L21/322 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02

    Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

    METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE
    18.
    发明申请
    METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 有权

    公开(公告)号：US20220139768A1

    公开(公告)日：2022-05-05

    申请号：US17435017

    申请日：2020-03-26

    Applicant: Soitec

    Inventor： Marcel Broekaart ,  Arnaud Castex

    IPC: H01L21/762

    Abstract: A method for fabricating a semiconductor-on-insulator structure involves providing a donor substrate comprising a weakened zone delimiting a layer to be transferred, providing a receiver substrate, and bonding the donor substrate to the receiver substrate. The layer to be transferred is located on the bonding-interface side. A bonding wave is initiated at a first region on the periphery of the interface, and the wave is propagated toward a second region on the periphery of the interface opposite the first region. The difference in speed of propagation of the bonding wave between a central portion of the interface and a peripheral portion of the interface is controlled such that the speed of propagation of the bonding wave is lower in the central portion than in the peripheral portion. The donor substrate is detached along the weakened zone to transfer the layer to be transferred to the receiver substrate.

    SEMICONDUCTOR-ON-INSULATOR SUBSTATE FOR RF APPLICATIONS
    19.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR SUBSTATE FOR RF APPLICATIONS 有权

    公开(公告)号：US20210057269A1

    公开(公告)日：2021-02-25

    申请号：US17090608

    申请日：2020-11-05

    Applicant: Soitec

    Inventor： Arnaud Castex ,  Oleg Kononchuk

    IPC: H01L21/762 ,  H01L21/02 ,  H01L27/12

    Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

    SEMICONDUCTOR-ON-INSULATOR SUBSTRATE FOR RF APPLICATIONS
    20.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR SUBSTRATE FOR RF APPLICATIONS 审中-公开

    公开(公告)号：US20190115248A1

    公开(公告)日：2019-04-18

    申请号：US16090349

    申请日：2017-03-30

    Applicant: Soitec

    Inventor： Arnaud Castex ,  Oleg Kononchuk

    IPC: H01L21/762 ,  H01L27/12 ,  H01L21/02

    Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

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