公开(公告)号：US09076713B2

公开(公告)日：2015-07-07

申请号：US13748146

申请日：2013-01-23

Applicant: Soitec ,  Commissariat à l'Énergie Atomique

Inventor： Thomas Signamarcheix ,  Frederic Allibert ,  Chrystel Deguet

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/58 ,  H01L29/16 ,  H01L21/318 ,  H01L21/762

CPC classification number: H01L29/16 ,  H01L21/318 ,  H01L21/76254 ,  H01L21/76283

Abstract: The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localized positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention.

Abstract translation: 本发明涉及一种用于制造局部钝化的绝缘体上的锗衬底的方法，其中为了获得良好的电子迁移率，在局部位置提供氮化区域。 使用等离子体处理实现氮化。 所得到的基底也构成本发明的一部分。

公开(公告)号：US20140225182A1

公开(公告)日：2014-08-14

申请号：US14253690

申请日：2014-04-15

Applicant: Soitec

Inventor： Mohamad A. Shaheen ,  Frederic Allibert ,  Gweltaz Gaudin ,  Fabrice Lallement ,  Didier Landru ,  Karine Landry ,  Carlos Mazure

IPC: H01L29/786

CPC classification number: H01L29/78603 ,  H01L29/32 ,  H01L29/7841 ,  H01L31/0248

Abstract: A substrate comprises a base wafer, an insulating layer over the base wafer, and a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer. The insulating layer comprises a charge-confining layer confined on one or both sides with diffusion barrier layers, wherein the charge-confining layer has a density of charges in absolute value higher than 1010 charges/cm2. Alternatively, the insulating layer comprises charge-trapping islands embedded therein, wherein the charge-trapping islands have a total density of charges in absolute value higher than 1010 charges/cm2.

Abstract translation: 衬底包括基底晶片，在基底晶片上方的绝缘层，以及在与基底晶片相对的一侧上的绝缘层上的顶部半导体层。 绝缘层包括限制在具有扩散阻挡层的一侧或两侧的电荷限制层，其中电荷限制层的绝对值的电荷密度高于1010电荷/ cm 2。 或者，绝缘层包括嵌入其中的电荷捕获岛，其中电荷捕获岛具有高于1010电荷/ cm 2的绝对值的电荷的总密度。

公开(公告)号：US10819282B2

公开(公告)日：2020-10-27

申请号：US16614732

申请日：2018-05-23

Applicant: Soitec

Inventor： Marcel Broekaart ,  Frederic Allibert ,  Eric Desbonnets ,  Jean-Pierre Raskin ,  Martin Rack

IPC: H01L23/66 ,  H03C7/00

Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.

公开(公告)号：US10002882B2

公开(公告)日：2018-06-19

申请号：US15176925

申请日：2016-06-08

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Frederic Allibert ,  Christophe Maleville

IPC: H01L21/425 ,  H01L27/12 ,  H01L21/265 ,  H01L21/84 ,  H01L21/266 ,  H01L23/66

CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/84 ,  H01L23/66

Abstract: A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency (RF) circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.

公开(公告)号：US08735946B2

公开(公告)日：2014-05-27

申请号：US14027528

申请日：2013-09-16

Applicant: Soitec

Inventor： Mohamad A Shaheen ,  Frederic Allibert ,  Gweltaz Gaudin ,  Fabrice Lallement ,  Didier Landru ,  Karine Landry ,  Carlos Mazure

IPC: H01L27/148

CPC classification number: H01L29/78603 ,  H01L29/32 ,  H01L29/7841 ,  H01L31/0248

Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.

Abstract translation: 本发明的实施例涉及包括基底晶片，绝缘层和顶部半导体层的基板，其中绝缘层至少包括电荷密度高于1010电荷/ cm 2的绝对值的区域。 本发明还涉及制造这种基材的方法。