公开(公告)号：US20150028920A1

公开(公告)日：2015-01-29

申请号：US14380312

申请日：2013-02-11

Applicant: SOITEC

Inventor： Richard Ferrant

IPC: H03K17/693 ,  H03K17/00 ,  H03K19/177

CPC classification number: H03K17/693 ,  H03K17/005 ,  H03K17/735 ,  H03K19/17728 ,  H03K2017/6878 ,  H03K2217/0018

Abstract: The present invention relates to a multiplexer comprising at least a first input and a second input and one output connected to the first input via a first pass gate and to the second input via a second pass gate, wherein the first pass gate comprises at least a first double-gate transistor, and the second pass gate comprises at least a second double-gate transistor, and each of the first and second double-gate transistors has a first gate controlled based on a first control signal and a second gate controlled based on a second control signal. The invention further relates to a look-up table and a and an FPGA based on the multiplexer.

Abstract translation: 多路复用器技术领域本发明涉及一种多路复用器，包括至少第一输入端和第二输入端和第一输出端，​​第一输入端和第一输出端经由第一通路栅极连接到第一输入端，并经由第二通路栅极连接到第二输入端， 第一双栅极晶体管，并且第二栅极包括至少第二双栅极晶体管，并且第一和第二双栅极晶体管中的每一个具有基于第一控制信号的第一栅极和基于第一栅极控制的第二栅极 第二控制信号。 本发明还涉及一种基于多路复用器的查找表和FPGA。

公开(公告)号：US20150022237A1

公开(公告)日：2015-01-22

申请号：US14381098

申请日：2013-02-11

Applicant: Soitec

Inventor： Richard Ferrant

IPC: H03K19/177

CPC classification number: H03K19/17728 ,  H03K19/17764

Abstract: The present invention relates to a look-up table comprising a plurality of register signals (r0-r3); a plurality of inputs signals (A, A′, B, B′); and at least one output signal (Y); and a plurality of pass gates, wherein at least a first pass gate of the plurality of pass gates is controlled by at least a first input signal of the plurality of input signals, and by at least a first register signal, of the plurality of register signals, such that the register signal has priority over the input signal on the operation of the first pass gate.

Abstract translation: 本发明涉及一种包括多个寄存器信号（r0-r3）的查找表; 多个输入信号（A，A'，B，B'）; 和至少一个输出信号（Y）; 以及多个通过门，其中所述多个通过门中的至少第一通过栅极由所述多个输入信号中的至少第一输入信号以及所述多个输入信号中的至少第一寄存器信号来控制 信号，使得寄存器信号在第一通过门的操作上优先于输入信号。

公开(公告)号：US08625374B2

公开(公告)日：2014-01-07

申请号：US13718571

申请日：2012-12-18

Applicant: Soitec

Inventor： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC: G11C7/00 ,  G11C11/4091

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/067 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2211/4016

Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.

Abstract translation: 一种用于存储器的一系列单元的读出放大器，包括一个写入级，它包括一个CMOS反相器，其输入直接或间接地连接到读出放大器的输入端，并且其输出端连接到输出端 所述读出放大器旨在连接到寻址该串联的单元的本地位线;以及读取级，其包括检测晶体管，其栅极连接到反相器的输出端，其漏极连接到 输入变频器。

公开(公告)号：US09621168B2

公开(公告)日：2017-04-11

申请号：US14381098

申请日：2013-02-11

Applicant: Soitec

Inventor： Richard Ferrant

IPC: H03K19/177

CPC classification number: H03K19/17728 ,  H03K19/17764

Abstract: The present invention relates to a look-up table comprising a plurality of register signals (r0-r3); a plurality of inputs signals (A, A′, B, B′); and at least one output signal (Y); and a plurality of pass gates, wherein at least a first pass gate of the plurality of pass gates is controlled by at least a first input signal of the plurality of input signals, and by at least a first register signal, of the plurality of register signals, such that the register signal has priority over the input signal on the operation of the first pass gate.

公开(公告)号：US20140376318A1

公开(公告)日：2014-12-25

申请号：US14372345

申请日：2013-01-16

Applicant: SOITEC

Inventor： Richard Ferrant ,  Roland Thewes

IPC: G11C7/08 ,  G11C11/4091 ,  G11C7/12

CPC classification number: G11C7/08 ,  G11C7/062 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

Abstract: a circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising: a pair of cross-coupled inverters arranged between the first and the second signal lines, each inverter having a pull-up transistor and a pull-down transistor, the sources of the pull-up transistors or of the pull-down transistors being respectively connected to a first and a second pull voltage signals, decode transistor having source and drain terminals respectively coupled to one of the first and second signal lines and a gate controlled by a decoding control signal, whereby when the decode transistor is turned on by the decoding control signal, a short circuit is established between the first and the second signal lines through which current flows from one of the first and second pull voltage signals, thereby generating a disturb in between the first and the second pull voltage signals.

Abstract translation: 用于检测包括与第一信号线互补的第一信号线和第二信号线的一对双信号线上的电压差的电路，包括：布置在第一和第二信号线之间的一对交叉耦合反相器 每个反相器具有上拉晶体管和下拉晶体管，上拉晶体管或下拉晶体管的源极分别连接到第一和第二拉电压信号，解码晶体管具有源极和漏极 分别耦合到第一和第二信号线之一的端子和由解码控制信号控制的门，由此当解码晶体管被解码控制信号导通时，在第一和第二信号线之间建立短路通过 该电流从第一和第二拉电压信号之一流动，从而在第一和第二拉电压信号之间产生干扰。

公开(公告)号：US20140321225A1

公开(公告)日：2014-10-30

申请号：US14358193

申请日：2012-11-14

Applicant: SOITEC

Inventor： Richard Ferrant ,  Joerg Vollrath ,  Roland Thewes ,  Wolfgang Hoenlein ,  Hofmann Franz ,  Gerhard Enders

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002

Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Abstract translation: 本发明涉及用于感测和放大存储在存储单元中的数据的读出放大器，该读出放大器连接在位线（BL）和与第一位线的基准位线互补（/ BL）之间，并且包括：感测 电路（SC）能够提供指示存储在存储单元中的数据的输出; 以及预充电和解码电路（PDC），包括一对双栅极晶体管（T5，T6），用于在预充电操作期间对第一和第二位线进行预充电，并将由感测电路提供的输出传送到数据线（LIO， / LIO）。

公开(公告)号：US09230662B2

公开(公告)日：2016-01-05

申请号：US14385436

申请日：2013-02-11

Applicant: Soitec

Inventor： Richard Ferrant

IPC: H03K19/177 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/045 ,  H03K19/1776

Abstract: The present invention relates to a register cell comprising one output node, at least two power supply nodes, and a first flash transistor and a second flash transistor, wherein the register cell is configured so that the output node can be driven by at least one of the power supply nodes as a function of the value stored in at least one of the flash transistors. The invention further relates to an FPGA comprising the register cell.

Abstract translation: 本发明涉及一种寄存器单元，包括一个输出节点，至少两个电源节点，以及第一闪存晶体管和第二闪存晶体管，其中该寄存器单元被配置为使得输出节点能够被至少一个 电源节点作为存储在至少一个闪存晶体管中的值的函数。 本发明还涉及包括寄存器单元的FPGA。

公开(公告)号：US09225237B2

公开(公告)日：2015-12-29

申请号：US14384129

申请日：2013-03-22

Applicant: Soitec

Inventor： Richard Ferrant

IPC: G05F1/10 ,  G05F3/02 ,  H02M3/07

CPC classification number: H02M3/07 ,  H02M3/073 ,  H02M2003/078

Abstract: The invention relates to a charge pump circuit comprising an input node for inputting a voltage to be boosted; an output node for outputting a boosted voltage; a plurality of pumping stages connected in series between the input node and the output node, each pump stage comprising at least one charge transfer transistor, wherein the at least one charge transfer transistor is a double-gate transistor comprising a first gate for turning the transistor on or off according to a first control signal applied to the first gate and a second gate for modifying the threshold voltage of the transistor according to a second control signal applied to the second gate, wherein the first and second control signals have the same phase.

Abstract translation: 本发明涉及一种电荷泵电路，其包括用于输入要升压的电压的输入节点; 用于输出升压电压的输出节点; 串联连接在所述输入节点和所述输出节点之间的多个泵浦级，每个泵级包括至少一个电荷转移晶体管，其中所述至少一个电荷转移晶体管是双栅极晶体管，包括用于转换晶体管的第一栅极 根据施加到第一栅极的第一控制信号的第一控制信号，以及施加到第二栅极的第二控制信号修改晶体管的阈值电压的第二栅极，其中第一和第二控制信号具有相同的相位。

公开(公告)号：US20150145049A1

公开(公告)日：2015-05-28

申请号：US14396665

申请日：2013-05-08

Applicant: Soitec

Inventor： Franz Hoffman ,  Richard Ferrant ,  Carlos Mazure

IPC: H01L27/108 ,  H01L27/092

CPC classification number: H01L27/10802 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7841

Abstract: The present invention relates to a floating body memory cell comprising: a first MOS transistor and a second MOS transistor, wherein at least the second MOS transistor has a floating body; and wherein the first and second MOS transistors are configured such that charges can be moved to/from the floating body of the second MOS transistor via the first MOS transistor.

Abstract translation: 本发明涉及一种浮体存储单元，包括：第一MOS晶体管和第二MOS晶体管，其中至少第二MOS晶体管具有浮体; 并且其中所述第一和第二MOS晶体管被配置为使得电荷可以经由所述第一MOS晶体管移动到所述第二MOS晶体管的浮体。