公开(公告)号：US08922265B1

公开(公告)日：2014-12-30

申请号：US14369652

申请日：2012-12-27

Applicant: Southeast University

Inventor： Na Bai ,  Longxing Shi ,  Jun Yang ,  Xinning Liu ,  Jiafeng Zhu ,  Yue Feng ,  Cai Gong ,  Fei Pan ,  Hong Chang ,  Yifeng Deng ,  Yuan Chen ,  Yingcheng Xia

IPC: H03L5/00 ,  H03K3/013 ,  H03K3/012

CPC classification number: H03K3/013 ,  G11C11/417 ,  G11C11/419 ,  H03K3/012

Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals. The current compensation circuit can be used for an SRAM bit line leakage current compensation circuit, because the existence of a large leakage current on the SRAM bit line leads to the decreasing of a voltage difference between two ends of the bit line, resulting in that a subsequent circuit cannot correctly identify a signal.

Abstract translation: 公开了一种噪声电流补偿电路。 该电路设有两个输入和输出端子A和B，以及两个控制端子CON和CONF。 控制端子控制补偿电路的工作模式（工作状态和预充电状态）。 补偿电路由7个PMOS晶体管和8个NMOS晶体管组成。 在正常工作状态下，通过检测原始电路中两根信号线的电位变化率的变化，噪声电流补偿电路自动使缓慢放电的原电路的一端缓慢放电，使一端 原始电路快速放电以更快地放电信号，从而消除噪声电流对电路的影响，并为后续电路信号的正确识别提供帮助。 电流补偿电路可以用于SRAM位线漏电流补偿电路，因为SRAM位线上存在大的漏电流导致位线两端之间的电压差减小，导致 后续电路无法正确识别信号。

公开(公告)号：US11196335B2

公开(公告)日：2021-12-07

申请号：US16968594

申请日：2020-04-30

Applicant: SOUTHEAST UNIVERSITY

Inventor： Chao Chen ,  Jun Yang ,  Xinning Liu

IPC: H02M1/00 ,  H02M3/07 ,  H03K3/037

Abstract: An ultra-low-power mode control circuit for a power converter includes four modules: a level shift circuit, a start circuit, a static clamp circuit, and a control circuit. When a chip is powered on and a core voltage has not been established, the control circuit firstly starts a power source built-in clock to support operation of the power converter. When the core voltage is established, the control circuit determines whether to switch to an external clock according to a level of a mode selection signal. After the core voltage is powered down, the control circuit automatically wakes up the built-in clock to work.

公开(公告)号：US20150331799A1

公开(公告)日：2015-11-19

申请号：US14430411

申请日：2013-11-13

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng Cao ,  Jun Yang ,  Longxing Shi ,  Bo Liu ,  Jinjiang Yang ,  Leibo Liu ,  Shouyi Yin ,  Shaojun Wei

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0862 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673 ,  G06F17/5054 ,  G06F2212/1041 ,  G06F2212/601 ,  G06F2212/602 ,  G06F2212/6028 ,  H04L67/2842

Abstract: Disclosed are a pre-decoding analysis-based configuration information cache management system, comprising a streaming media processing module, a configuration information prefetch FIFO module, a configuration information storage unit, and a cache controller module. Also disclosed is a management method for the pre-decoding analysis-based configuration information cache management system. The present invention allows for increased dynamic reconfiguration efficiency of a large-scale coarse-grained reconfigurable system.

Abstract translation: 公开了一种基于预解码分析的配置信息高速缓存管理系统，其包括流媒体处理模块，配置信息预取FIFO模块，配置信息存储单元和高速缓存控制器模块。 还公开了一种用于基于预解码分析的配置信息高速缓存管理系统的管理方法。 本发明允许增加大规模粗粒度可重构系统的动态重配置效率。

公开(公告)号：US12112243B2

公开(公告)日：2024-10-08

申请号：US17043715

申请日：2019-03-12

Applicant: Southeast University

Inventor： Peng Cao ,  Bingqian Xu ,  Jingjing Guo ,  Mengxiao Li ,  Jun Yang

IPC: G06N20/00 ,  G01R31/28

CPC classification number: G06N20/00 ,  G01R31/2882

Abstract: A method for predicting the fluctuation of circuit path delay on the basis of machine learning, comprising the following steps: S1: selecting suitable sample characteristics by means of analyzing the relationship between circuit characteristics and path delay; S2: generating a random path by means of enumerating values of randomized parameters, acquiring the maximum path delay by means of performing Monte Carlo simulation on the random path, selecting a reliable path by means of the 3σ standard, and using the sample characteristics and path delay of the reliable path as a sample set (D); S3: establishing a path delay prediction model, and adjusting parameters of the model; S4: verifying the precision and stability of the path delay prediction model; S5: obtaining the path delay. The method for predicting the fluctuation of circuit path delay on the basis of machine learning has the advantages of high precision and low running time, thereby having remarkable advantages in the accuracy and efficiency of timing analysis.

公开(公告)号：US10984313B2

公开(公告)日：2021-04-20

申请号：US16757421

申请日：2019-01-24

Applicant: Southeast University

Inventor： Bo Liu ,  Yu Gong ,  Wei Ge ,  Jun Yang ,  Longxing Shi

IPC: G06N3/063 ,  G06F7/50 ,  G06F7/523 ,  G06F7/544 ,  G06N3/08

Abstract: The present invention relates to the field of analog integrated circuits, and provides a multiply-accumulate calculation method and circuit suitable for a neural network, which realizes large-scale multiply-accumulate calculation of the neural network with low power consumption and high speed. The multiply-accumulate calculation circuit comprises a multiplication calculation circuit array and an accumulation calculation circuit. The multiplication calculation circuit array is composed of M groups of multiplication calculation circuits. Each group of multiplication calculation circuits is composed of one multiplication array unit and eight selection-shift units. The order of the multiplication array unit is quantized in real time by using on-chip training to provide a shared input for the selection-shift units, achieving increased operating rate and reduced power consumption. The accumulation calculation circuit is composed of a delay accumulation circuit, a TDC conversion circuit, and a shift-addition circuit in series. The delay accumulation circuit comprises eight controllable delay chains for dynamically controlling the number of iterations and accumulating data multiple times in a time domain, so as to meet the difference in calculation scale of different network layers, save hardware storage space, reduce calculation complexity, and reduce data scheduling.

公开(公告)号：US10422830B2

公开(公告)日：2019-09-24

申请号：US15321111

申请日：2014-12-26

Applicant: Southeast University

Inventor： Weiwei Shan ,  Longxing Shi ,  Jun Yang

IPC: G01R31/28 ,  H03K3/03

Abstract: A process corner detection circuit based on a self-timing ring oscillator comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing ring oscillator (2) consists of m two-input Muller C-elements and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing ring oscillator (2). The number of oscillations of the self-timing ring oscillator (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.

公开(公告)号：US10268790B2

公开(公告)日：2019-04-23

申请号：US15560161

申请日：2017-02-24

Applicant: Southeast University

Inventor： Weiwei Shan ,  Wentao Dai ,  Jun Yang ,  Longxing Shi

IPC: G06F17/50 ,  H03K5/19 ,  H03K5/1534

Abstract: An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, present invention eliminates a need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing an area and a power consumption of the online monitoring unit significantly and improving an energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, a time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by process-voltage-temperature (PVT) variations, thus enabling a minimization of a timing margin and ensuring a higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.

公开(公告)号：US20150254180A1

公开(公告)日：2015-09-10

申请号：US14425456

申请日：2013-11-13

Applicant: Southeast University

Inventor： Longxing Shi ,  Jun Yang ,  Peng Cao ,  Bo Liu ,  Jinjiang Yang ,  Leibo Liu ,  Shouyi Yin ,  Shaojun Wei

IPC: G06F12/06 ,  G06F12/08

CPC classification number: G06F12/0646 ,  G06F12/0811 ,  G06F12/0895 ,  G06F17/5054 ,  G06F2212/283 ,  G06F2212/601

Abstract: Disclosed is a cache structure for use in implementing reconfigurable system configuration information storage, comprising: layered configuration information cache units: for use in caching configuration information that may be used by a certain or several reconfigurable arrays within a period of time; an off-chip memory interface module: for use in establishing communication; a configuration anagement unit: for use in managing a reconfiguration process of the reconfigurable arrays, in mapping each subtask in an algorithm application to a certain reconfigurable array, thus the reconfigurable array will, on the basis of the mapped subtask, load the corresponding configuration information to complete a function reconfiguration for the reconfigurable array. This increases the utilization efficiency of configuration information caches. Also provided is a method for managing the reconfigurable system configuration information caches, employing a mixed priority cache update method, and changing a mode for managing the configuration information caches in a conventional reconfigurable system, thus increasing the dynamic reconfiguration efficiency in a complex reconfigurable system.

Abstract translation: 公开了一种用于实现可重构系统配置信息存储的缓存结构，包括：分层配置信息高速缓存单元：用于缓存在一段时间内由特定或多个可重配置阵列使用的配置信息; 片外存储器接口模块：用于建立通信; 配置管理单元：用于管理可重新配置阵列的重新配置过程，将算法应用中的每个子任务映射到某个可重配置阵列，因此可重构阵列将基于映射子任务加载相应的配置信息 完成可重构阵列的功能重新配置。 这增加了配置信息高速缓存的使用效率。 还提供了一种用于管理可重配置系统配置信息高速缓存的方法，采用混合优先级高速缓存更新方法，以及改变用于管理常规可重新配置系统中的配置信息高速缓存的模式，从而增加复杂可重新配置系统中的动态重新配置效率。

公开(公告)号：US20140376305A1

公开(公告)日：2014-12-25

申请号：US14369651

申请日：2012-12-27

Applicant: SOUTHEAST UNIVERSITY

Inventor： Na Bai ,  Longxing Shi ,  Jun Yang ,  Xinning Liu ,  Jiafeng Zhu ,  Yue Feng ,  Cai Gong ,  Fei Pan ,  Hong Chang ,  Yifeng Deng ,  Yuan Chen ,  Yingcheng Xia

IPC: G11C11/419 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/417 ,  H01L27/1104

Abstract: The present invention discloses a circuit for improving process robustness of sub-threshold SRAM memory cells, which serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to the PMOS tube of the sub-threshold SRAM memory cell and the substrate of a PMOS tube in the circuit. The circuit comprises a detection circuit for threshold voltage of PMOS tube and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS tubes in the sub-threshold SRAM memory cell and the substrate voltage of the PMOS tube in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS tubes and NMOS tubes resulted from process fluctuations and thereby regulate the threshold voltages of the PMOS tubes, so that the threshold voltage of PMOS tubes matches the threshold voltage of NMOS tubes. The circuit improves the noise margin of sub-threshold SRAM memory cells and effectively improves the process robustness of sub-threshold SRAM memory cells.

Abstract translation: 本发明公开了一种用于提高亚阈值SRAM存储单元的处理鲁棒性的电路，其用作子阈值SRAM存储单元的辅助电路。 电路的输出连接到子阈值SRAM存储单元的PMOS管和电路中的PMOS管的衬底。 该电路包括用于PMOS管的阈值电压的检测电路和差分输入和单端输出放大器。 该电路通过检测来自过程波动的PMOS管和NMOS管的阈值电压波动，以自适应方式改变子阈值SRAM存储单元中的PMOS管的衬底电压和电路中的PMOS管的衬底电压 从而调节PMOS管的阈值电压，使得PMOS管的阈值电压与NMOS管的阈值电压相匹配。 该电路提高了亚阈值SRAM存储单元的噪声容限，有效提高了亚阈值SRAM存储单元的工艺稳健性。

公开(公告)号：US12141682B2

公开(公告)日：2024-11-12

申请号：US17181595

申请日：2021-02-22

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei Shan ,  Ziyu Li ,  Jun Yang ,  Longxing Shi

IPC: G06N3/063 ,  G06N3/04 ,  G06F119/12

Abstract: The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under “negative margin”, the system can further lower voltage, compress the timing slack, and obtain higher power gain.