公开(公告)号：US20080122452A1

公开(公告)日：2008-05-29

申请号：US12028451

申请日：2008-02-08

申请人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford ,  Vernon R. Norman

发明人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford ,  Vernon R. Norman

IPC分类号： G01R35/00

CPC分类号： G01R35/007 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174

摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

公开(公告)号：US08704583B2

公开(公告)日：2014-04-22

申请号：US13399054

申请日：2012-02-17

申请人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

发明人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

IPC分类号： H03L5/00 ,  H03F3/45

CPC分类号： H03F1/0261 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45197 ,  H03F3/45632 ,  H03F2200/27 ,  H03F2203/45631 ,  H03K19/018528

摘要： Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.

摘要翻译： 提供电容电平移位电路和方法用于将直流偏移添加到电流积分放大器的输出。 例如，电流积分放大器包括输入放大器级和输出偏移电路。 输入放大器级包括输入节点，第一输出节点和连接在第一输出节点和电源节点之间的第一开关。 输出偏移电路连接到输入放大器级的第一输出节点和电流积分放大器的第二输出节点。 输出偏移电路包括耦合在输入放大器级的第一输出节点和电流积分放大器的第二输出节点之间的第一串联电容器。 输出偏移电路将偏置电压切换到第二输出节点并对第一串联电容器充电，以向电流积分放大器的第二输出节点添加DC偏移。

公开(公告)号：US20130214865A1

公开(公告)日：2013-08-22

申请号：US13399054

申请日：2012-02-17

申请人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

发明人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

IPC分类号： H03F3/45

CPC分类号： H03F1/0261 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45197 ,  H03F3/45632 ,  H03F2200/27 ,  H03F2203/45631 ,  H03K19/018528

摘要： Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.

摘要翻译： 提供电容电平移位电路和方法用于将直流偏移添加到电流积分放大器的输出。 例如，电流积分放大器包括输入放大器级和输出偏移电路。 输入放大器级包括输入节点，第一输出节点和连接在第一输出节点和电源节点之间的第一开关。 输出偏移电路连接到输入放大器级的第一输出节点和电流积分放大器的第二输出节点。 输出偏移电路包括耦合在输入放大器级的第一输出节点和电流积分放大器的第二输出节点之间的第一串联电容器。 输出偏移电路将偏置电压切换到第二输出节点并对第一串联电容器充电，以向电流积分放大器的第二输出节点添加DC偏移。

公开(公告)号：US20150099285A1

公开(公告)日：2015-04-09

申请号：US14462143

申请日：2014-08-18

申请人： Steven M. Clements ,  Richard L. Clements

发明人： Steven M. Clements ,  Richard L. Clements

IPC分类号： C10G1/04 ,  C10L1/02 ,  H02K7/18 ,  C10L1/00

CPC分类号： H02K7/1807 ,  C10L1/023 ,  C10L1/026 ,  C10L2200/0476 ,  C10L2270/026 ,  Y02E50/13

摘要： The present invention relates to systems and methods for producing energy. Specifically, the present invention relates to systems and methods for producing energy, such as energy in the form of electricity, and fuels, such as, for example, biodiesel and/or cellulosic ethanol in a small scale energy center. Moreover, the systems and methods of the present invention provide for recovery of materials, such as in soil production and/or recycling.

摘要翻译： 本发明涉及用于生产能量的系统和方法。 具体地，本发明涉及用于生产能量的系统和方法，例如在电力形式中的能量，以及燃料，例如在小规模能量中心的生物柴油和/或纤维素乙醇。 此外，本发明的系统和方法提供材料的回收，例如在土壤生产和/或回收中。

公开(公告)号：US20090189654A1

公开(公告)日：2009-07-30

申请号：US12019748

申请日：2008-01-25

申请人： Steven M. Clements ,  Todd M. Rasmus

发明人： Steven M. Clements ,  Todd M. Rasmus

IPC分类号： H03L7/06

CPC分类号： H03L7/0895

摘要： A method, system, and circuit design product for setting the common-mode voltage level of a charge pump to yield low duty cycle distortion from a voltage controlled oscillator (VCO). Differential charge pumps utilize common-mode feedback (CMF) networks to control the common-mode voltage level. A replica circuit of a current starved delay cell from a VCO replaces the unity gain buffering circuit within a common-mode feedback circuit. Inserting the current starved delay cell replica circuit permits adequate negative feedback compensation, while allowing a phase locked loop (PLL) to operate with a wide bandwidth. As a result of utilizing the replica circuit of a current starved delay cell from a VCO, the common-mode voltage level is optimally centered to interface with the VCO, thereby minimizing duty cycle distortion.

摘要翻译： 一种用于设置电荷泵的共模电压电平以从压控振荡器（VCO）产生低占空比失真的方法，系统和电路设计产品。 差分电荷泵利用共模反馈（CMF）网络来控制共模电压电平。 来自VCO的当前饥饿延迟单元的复制电路替代共模反馈电路内的单位增益缓冲电路。 插入当前受饥饿的延迟单元复制电路允许充分的负反馈补偿，同时允许锁相环（PLL）以宽带宽工作。 作为利用来自VCO的当前饥饿延迟单元的复制电路的结果，共模电压电平被最佳地集中于与VCO的接口，从而最小化占空比失真。

公开(公告)号：US07750744B2

公开(公告)日：2010-07-06

申请号：US12019763

申请日：2008-01-25

申请人： Steven M. Clements ,  Todd M. Rasmus

发明人： Steven M. Clements ,  Todd M. Rasmus

IPC分类号： H03B27/00

CPC分类号： H03L7/0995 ,  H03L7/0891

摘要： A method, system, and circuit device for interfacing single-ended charge pump output to differential voltage controlled oscillator (VCO) inputs to yield low duty cycle distortion from a VCO. A single-ended charge pump output is utilized to create a compliment differential voltage leg, while optimally centering the common-mode voltage level to interface to a current starved ring VCO. A replica of the VCO's current starved delay cell is implemented along with negative feedback to generate the compliment differential voltage leg. The single-ended charge pump output is coupled to a first transistor, while a second transistor is coupled to the output of an error amplifier. The error amplifier utilizes negative feedback to bias the second transistor, forcing the output of the replica circuit to equal a reference voltage.

摘要翻译： 一种用于将单端电荷泵输出连接到差分压控振荡器（VCO）输入的方法，系统和电路装置，以产生来自VCO的低占空比失真。 使用单端电荷泵输出来产生补偿差分电压支路，同时将共模电压电平最佳地对准到当前饥饿环形VCO的接口。 VCO的当前饥饿延迟单元的副本与负反馈一起实现以产生补偿差分电压支路。 单端电荷泵输出耦合到第一晶体管，而第二晶体管耦合到误差放大器的输出端。 误差放大器利用负反馈来偏置第二晶体管，迫使复制电路的输出等于参考电压。

公开(公告)号：US20090189701A1

公开(公告)日：2009-07-30

申请号：US12019763

申请日：2008-01-25

申请人： Steven M. Clements ,  Todd M. Rasmus

发明人： Steven M. Clements ,  Todd M. Rasmus

IPC分类号： H03L7/085 ,  H03L7/08

CPC分类号： H03L7/0995 ,  H03L7/0891

摘要： A method, system, and circuit device for interfacing single-ended charge pump output to differential voltage controlled oscillator (VCO) inputs to yield low duty cycle distortion from a VCO. A single-ended charge pump output is utilized to create a compliment differential voltage leg, while optimally centering the common-mode voltage level to interface to a current starved ring VCO. A replica of the VCO's current starved delay cell is implemented along with negative feedback to generate the compliment differential voltage leg. The single-ended charge pump output is coupled to a first transistor, while a second transistor is coupled to the output of an error amplifier. The error amplifier utilizes negative feedback to bias the second transistor, forcing the output of the replica circuit to equal a reference voltage.

摘要翻译： 一种用于将单端电荷泵输出连接到差分压控振荡器（VCO）输入的方法，系统和电路装置，以产生来自VCO的低占空比失真。 使用单端电荷泵输出来产生补偿差分电压支路，同时将共模电压电平最佳地对准到当前饥饿环形VCO的接口。 VCO的当前饥饿延迟单元的副本与负反馈一起实现以产生补偿差分电压支路。 单端电荷泵输出耦合到第一晶体管，而第二晶体管耦合到误差放大器的输出端。 误差放大器利用负反馈来偏置第二晶体管，迫使复制电路的输出等于参考电压。

公开(公告)号：US08139700B2

公开(公告)日：2012-03-20

申请号：US12492419

申请日：2009-06-26

申请人： Troy J. Beukema ,  Steven M. Clements ,  Chun-Ming Hsu ,  William R. Kelly ,  Elizabeth M. May ,  Sergey V. Rylov

发明人： Troy J. Beukema ,  Steven M. Clements ,  Chun-Ming Hsu ,  William R. Kelly ,  Elizabeth M. May ,  Sergey V. Rylov

IPC分类号： H04L25/00

CPC分类号： H03K5/1565 ,  H03K5/15013 ,  H03K2005/00052

摘要： A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.

摘要翻译： 用于闭环时钟校正的系统和方法包括调整包括至少一个同相时钟和一个正交时钟的两个或更多个输入信号，并将调整的正交时钟信号应用于能够产生4象限内插输出时钟相位的器件。 内插输出时钟相位被延迟以形成用于测量设备的时钟。 在内插输出时钟相位的范围内，在测量装置上测量两个或多个调整后的输入信号。 使用来自测量装置的采样信息，在同相时钟和正交时钟上确定错误。 使用确定的误差信息适配同相时钟和正交时钟。

公开(公告)号：US20100329403A1

公开(公告)日：2010-12-30

申请号：US12492419

申请日：2009-06-26

申请人： Troy J. Beukema ,  Steven M. Clements ,  Chun-Ming Hsu ,  William R. Kelly ,  Elizabeth M. May ,  Sergey V. Rylov

发明人： Troy J. Beukema ,  Steven M. Clements ,  Chun-Ming Hsu ,  William R. Kelly ,  Elizabeth M. May ,  Sergey V. Rylov

IPC分类号： H04L7/00

CPC分类号： H03K5/1565 ,  H03K5/15013 ,  H03K2005/00052

摘要： A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.

摘要翻译： 用于闭环时钟校正的系统和方法包括调整包括至少一个同相时钟和一个正交时钟的两个或更多个输入信号，并将调整的正交时钟信号应用于能够产生4象限内插输出时钟相位的器件。 内插输出时钟相位被延迟以形成用于测量设备的时钟。 在内插输出时钟相位的范围内，在测量装置上测量两个或多个调整后的输入信号。 使用来自测量装置的采样信息，在同相时钟和正交时钟上确定错误。 使用确定的误差信息适配同相时钟和正交时钟。

公开(公告)号：US07705640B2

公开(公告)日：2010-04-27

申请号：US12019748

申请日：2008-01-25

申请人： Steven M. Clements ,  Todd M. Rasmus

发明人： Steven M. Clements ,  Todd M. Rasmus

IPC分类号： H03L7/06

CPC分类号： H03L7/0895

摘要： A method, system, and circuit design product for setting the common-mode voltage level of a charge pump to yield low duty cycle distortion from a voltage controlled oscillator (VCO). Differential charge pumps utilize common-mode feedback (CMF) networks to control the common-mode voltage level. A replica circuit of a current starved delay cell from a VCO replaces the unity gain buffering circuit within a common-mode feedback circuit. Inserting the current starved delay cell replica circuit permits adequate negative feedback compensation, while allowing a phase locked loop (PLL) to operate with a wide bandwidth. As a result of utilizing the replica circuit of a current starved delay cell from a VCO, the common-mode voltage level is optimally centered to interface with the VCO, thereby minimizing duty cycle distortion.

摘要翻译： 一种用于设置电荷泵的共模电压电平以从压控振荡器（VCO）产生低占空比失真的方法，系统和电路设计产品。 差分电荷泵利用共模反馈（CMF）网络来控制共模电压电平。 来自VCO的当前饥饿延迟单元的复制电路替代共模反馈电路内的单位增益缓冲电路。 插入当前受饥饿的延迟单元复制电路允许充分的负反馈补偿，同时允许锁相环（PLL）以宽带宽工作。 作为利用来自VCO的当前饥饿延迟单元的复制电路的结果，共模电压电平被最佳地集中于与VCO的接口，从而最小化占空比失真。