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11.
公开(公告)号:US20140325247A1
公开(公告)日:2014-10-30
申请号:US13870195
申请日:2013-04-25
申请人: Inder Sodhi , Sanjeev Jahagirdar , Ryan Wells , Zeev Offen , Shalini Sharma , Ken Drottar
发明人: Inder Sodhi , Sanjeev Jahagirdar , Ryan Wells , Zeev Offen , Shalini Sharma , Ken Drottar
CPC分类号: G06F1/32 , G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要: In an embodiment, a processor includes a core to execute instructions, an agent to perform an operation independently of the core, a fabric to couple the core and agent and including a plurality of domains and a logic to receive isochronous parameter information from the agent and environmental information of a platform and to generate first and second values, and a power controller to control a frequency of the domains based at least in part on the first and second values. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,处理器包括执行指令的核心,独立于核心执行操作的代理,耦合核心和代理的结构,并且包括多个域以及从代理接收等时参数信息的逻辑,以及 平台的环境信息并产生第一和第二值,以及功率控制器,至少部分地基于第一和第二值来控制域的频率。 描述和要求保护其他实施例。
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公开(公告)号:US20130207987A1
公开(公告)日:2013-08-15
申请号:US13844214
申请日:2013-03-15
申请人: Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人: Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号: G06T1/60
CPC分类号: G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
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公开(公告)号:US20130173902A1
公开(公告)日:2013-07-04
申请号:US13342023
申请日:2011-12-31
申请人: Inder M. Sodhi , Amjad M. Khan , Zeev Offen , Ryan D. Wells
发明人: Inder M. Sodhi , Amjad M. Khan , Zeev Offen , Ryan D. Wells
CPC分类号: G06F1/3296 , G06F1/3243 , G06F1/3287 , G06F8/52 , G06F9/3017 , G06F9/3877 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要: I/O logic can be separated into critical and non-critical portions, with the non-critical portions being powered down during processor idle. The I/O logic is separated into gate logic and ungated logic, where the ungated logic continues to be powered during a processor deep sleep state, and the gated logic is powered off during the deep sleep state. A power control unit can trigger the shutting down of the I/O logic.
摘要翻译: I / O逻辑可以分为关键部分和非关键部分,非关键部分在处理器空闲期间关闭。 I / O逻辑分为门逻辑和非门逻辑,其中非门逻辑在处理器深度睡眠状态期间继续供电,并且门控逻辑在深度睡眠状态期间断电。 电源控制单元可以触发I / O逻辑的关闭。
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公开(公告)号:US20150178091A1
公开(公告)日:2015-06-25
申请号:US14139798
申请日:2013-12-23
申请人: Zeev Offen , Inder M. Sodhi
发明人: Zeev Offen , Inder M. Sodhi
CPC分类号: G06F9/3861 , G06F1/3287 , Y02D10/171
摘要: Processor context save latency is reduced by only restoring context registers with saved state that differs from the reset value of registers. A system agent monitors access to the design blocks and sets a dirty bit to indicate which design block has registers that have changed since the last context save. During a context save operation, the system agent bypasses design blocks that have not had context changes since the latest context save operation. During a context restore operation the system agent does not restore the context registers with saved context values that are equal to the reset value of the context register.
摘要翻译: 处理器上下文保存延迟仅通过恢复具有与寄存器的复位值不同的保存状态的上下文寄存器来减少。 系统代理监视对设计块的访问,并设置脏位,以指示哪个设计块具有自上一个上下文保存以来已更改的寄存器。 在上下文保存操作期间,系统代理绕过自最新上下文保存操作以来没有上下文更改的设计块。 在上下文恢复操作期间,系统代理不使用等于上下文寄存器的复位值的保存的上下文值来还原上下文寄存器。
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15.
公开(公告)号:US20140281380A1
公开(公告)日:2014-09-18
申请号:US13795338
申请日:2013-03-12
申请人: Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
发明人: Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
IPC分类号: G06F15/76
CPC分类号: G06F9/30123 , G06F1/32 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/461 , Y02D10/152 , Y02D10/171
摘要: Remapping technologies for execution context swap between heterogeneous functional hardware units are described. A computing system includes multiple registers configured to store remote contexts of functional units. A mapping table maps the remote context to the functional units. An execution unit is configured to execute a remapping tool that intercepts an operation to access a remote context of a first functional unit of the plurality of functional units that is taken offline. The remapping tool determines that the first functional unit is remapped to a second functional unit using the mapping table. The operation is performed to access the remote context that is remapped to the second functional unit. The first functional unit and the second functional unit may be heterogeneous functional units.
摘要翻译: 描述用于异构功能硬件单元之间执行上下文交换的重新映射技术。 计算系统包括配置成存储功能单元的远程上下文的多个寄存器。 映射表将远程上下文映射到功能单元。 执行单元被配置为执行重新映射工具,该重新映射工具拦截用于访问脱机的多个功能单元中的第一功能单元的远程上下文的操作。 重新映射工具确定使用映射表将第一功能单元重新映射到第二功能单元。 执行操作以访问被重新映射到第二功能单元的远程上下文。 第一功能单元和第二功能单元可以是异构功能单元。
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公开(公告)号:US20100235320A1
公开(公告)日:2010-09-16
申请号:US12401499
申请日:2009-03-10
CPC分类号: G06F12/0804 , G06F12/0811 , G06F2212/302 , Y02D10/13
摘要: A platform may comprise a core coherency domain, graphics coherency domain and a non-coherent domain. A graphics acceleration unit (GAU) of the graphics coherency domain may generate data units from an application and the data units may comprise display data units. The GAU may annotate the display data units with an annotation value before flushing the display data units to an on-die cache. The GAU may identify modified display data units among the display data units stored in the on-die cache and issue flush commands to cause flushing of the modified display data units from the on-die cache to a main memory. The display engine of the non-coherent domain may use the modified display data units stored in the main memory to render a display on a display device.
摘要翻译: 平台可以包括核心一致性域,图形一致性域和非相干域。 图形一致性域的图形加速单元(GAU)可以从应用产生数据单元,并且数据单元可以包括显示数据单元。 GAU可以在将显示数据单元刷新到片上高速缓存之前用注释值来注释显示数据单元。 GAU可以识别存储在片上高速缓存中的显示数据单元中的修改的显示数据单元,并发出刷新命令,以使经修改的显示数据单元从模块缓存刷新到主存储器。 非相干域的显示引擎可以使用存储在主存储器中的修改的显示数据单元在显示设备上呈现显示。
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公开(公告)号:US20100161907A1
公开(公告)日:2010-06-24
申请号:US12338919
申请日:2008-12-18
申请人: Geeyarpuram N. Santhanakrishnan , Julius Mandelblat , Ehud Cohen , Larisa Novakovsky , Zeev Offen , Michelle J. Moravan , Shlomo Raikin , Ron Gabor
发明人: Geeyarpuram N. Santhanakrishnan , Julius Mandelblat , Ehud Cohen , Larisa Novakovsky , Zeev Offen , Michelle J. Moravan , Shlomo Raikin , Ron Gabor
IPC分类号: G06F12/08
CPC分类号: G06F12/0808 , G06F12/0811 , G06F12/0815
摘要: A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.
摘要翻译: 处理器可以包括核心区域,控制单元,无孔区域。 核心区域可以包括多个处理核心和线填充缓冲器。 核心区域的第一处理核心可以将第一弱排序事务存储在第一行填充缓冲器中。 最初的处理核心可以在收到来自无孔区域的请求之后将第一弱有序的事务卸载到在非空区域中提供的扩展缓冲区。 然后,第一处理核心可以在第一弱有序事务被卸载到扩展缓冲区空间之后,将第一行填充缓冲区去分配。 然后,无节点可以将第一弱排序事务发布到存储器或存储器系统。 控制单元可以跟踪第一弱排序事务,以确保第一弱排序事务被发布到存储器或系统。
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18.
公开(公告)号:US20090248983A1
公开(公告)日:2009-10-01
申请号:US12057601
申请日:2008-03-28
申请人: Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人: Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号: G06F12/08
CPC分类号: G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译: 一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。 在一个实施例中,图形设备可以使用一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息,这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问 图形设备。
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19.
公开(公告)号:US09250901B2
公开(公告)日:2016-02-02
申请号:US13795338
申请日:2013-03-12
申请人: Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
发明人: Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
CPC分类号: G06F9/30123 , G06F1/32 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/461 , Y02D10/152 , Y02D10/171
摘要: Remapping technologies for execution context swap between heterogeneous functional hardware units are described. A computing system includes multiple registers configured to store remote contexts of functional units. A mapping table maps the remote context to the functional units. An execution unit is configured to execute a remapping tool that intercepts an operation to access a remote context of a first functional unit of the plurality of functional units that is taken offline. The remapping tool determines that the first functional unit is remapped to a second functional unit using the mapping table. The operation is performed to access the remote context that is remapped to the second functional unit. The first functional unit and the second functional unit may be heterogeneous functional units.
摘要翻译: 描述用于异构功能硬件单元之间执行上下文交换的重新映射技术。 计算系统包括配置成存储功能单元的远程上下文的多个寄存器。 映射表将远程上下文映射到功能单元。 执行单元被配置为执行重新映射工具,该重新映射工具拦截用于访问脱机的多个功能单元中的第一功能单元的远程上下文的操作。 重新映射工具确定使用映射表将第一功能单元重新映射到第二功能单元。 执行操作以访问被重新映射到第二功能单元的远程上下文。 第一功能单元和第二功能单元可以是异构功能单元。
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公开(公告)号:US20150177801A1
公开(公告)日:2015-06-25
申请号:US14140219
申请日:2013-12-24
申请人: Ivan Herrera Mejia , Zeev Offen
发明人: Ivan Herrera Mejia , Zeev Offen
CPC分类号: G06F1/26 , G06F1/24 , G06F1/324 , G06F1/3243 , G06F1/3296 , G06F9/24 , G06F9/4418 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要: Embodiments including systems, methods, and apparatuses associated providing an interface between a north complex and a south complex of a system on a chip (SoC). In embodiments, the north complex may include a microcontroller in an input signal requirement. A power-on control block may be coupled with the microcontroller, and the power-on control block may be configured to receive a control signal from a component of the south complex, and alter the control signal based at least in part on the input signal requirement of the microcontroller.
摘要翻译: 包括相关联的系统,方法和装置的实施例,其提供了芯片上的系统(SoC)的北复合体和南复合体之间的接口。 在实施例中,北复合体可以包括输入信号要求中的微控制器。 上电控制块可以与微控制器耦合,并且上电控制块可以被配置为从南复合体的组件接收控制信号,并且至少部分地基于输入信号来改变控制信号 要求微控制器。
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