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公开(公告)号：US20100161907A1
公开(公告)日：2010-06-24
申请号：US12338919
申请日：2008-12-18
申请人： Geeyarpuram N. Santhanakrishnan , Julius Mandelblat , Ehud Cohen , Larisa Novakovsky , Zeev Offen , Michelle J. Moravan , Shlomo Raikin , Ron Gabor
发明人： Geeyarpuram N. Santhanakrishnan , Julius Mandelblat , Ehud Cohen , Larisa Novakovsky , Zeev Offen , Michelle J. Moravan , Shlomo Raikin , Ron Gabor
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0811 , G06F12/0815
摘要： A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.
摘要翻译： 处理器可以包括核心区域，控制单元，无孔区域。 核心区域可以包括多个处理核心和线填充缓冲器。 核心区域的第一处理核心可以将第一弱排序事务存储在第一行填充缓冲器中。 最初的处理核心可以在收到来自无孔区域的请求之后将第一弱有序的事务卸载到在非空区域中提供的扩展缓冲区。 然后，第一处理核心可以在第一弱有序事务被卸载到扩展缓冲区空间之后，将第一行填充缓冲区去分配。 然后，无节点可以将第一弱排序事务发布到存储器或存储器系统。 控制单元可以跟踪第一弱排序事务，以确保第一弱排序事务被发布到存储器或系统。
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公开(公告)号：US08347035B2
公开(公告)日：2013-01-01
申请号：US12338919
申请日：2008-12-18
申请人： Geeyarpuram N. Santhanakrishnan , Julius Mandelblat , Ehud Cohen , Larisa Novakovsky , Zeev Offen , Michelle J. Moravan , Shlomo Raikin , Ron Gabor
发明人： Geeyarpuram N. Santhanakrishnan , Julius Mandelblat , Ehud Cohen , Larisa Novakovsky , Zeev Offen , Michelle J. Moravan , Shlomo Raikin , Ron Gabor
IPC分类号： G06F12/00
CPC分类号： G06F12/0808 , G06F12/0811 , G06F12/0815
摘要： A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.
摘要翻译： 处理器可以包括核心区域，控制单元，无孔区域。 核心区域可以包括多个处理核心和线填充缓冲器。 核心区域的第一处理核心可以将第一弱排序事务存储在第一行填充缓冲器中。 最初的处理核心可以在收到来自无孔区域的请求之后将第一弱有序的事务卸载到在非空区域中提供的扩展缓冲区。 然后，第一处理核心可以在第一弱有序事务被卸载到扩展缓冲区空间之后，将第一行填充缓冲区去分配。 然后，无节点可以将第一弱排序事务发布到存储器或存储器系统。 控制单元可以跟踪第一弱排序事务，以确保第一弱排序事务被发布到存储器或系统。
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公开(公告)号：US09448879B2
公开(公告)日：2016-09-20
申请号：US13994105
申请日：2011-12-22
申请人： Theodros Yigzaw , Oded Lempel , Hisham Shafi , Geeyarpuram N. Santhanakrishnan , Jose A. Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Mandelblat , Michael Mishaeli
发明人： Theodros Yigzaw , Oded Lempel , Hisham Shafi , Geeyarpuram N. Santhanakrishnan , Jose A. Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Mandelblat , Michael Mishaeli
CPC分类号： G06F11/1064 , G06F11/0793 , G06F11/1016 , G06F11/1407
摘要： An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.
摘要翻译： 描述了用于检测和校正处理器核心内的指令获取错误的装置和方法。 例如，在一个实施例中，用于从指令获取错误中检测和恢复的指令处理装置包括：指令处理装置执行以下操作：响应于指令提取操作检测与指令相关联的错误; 以及确定所述指令是否来自投机访问，其中如果所述指令不是来自投机访问，则响应地执行一个或多个操作以确保所述错误不会破坏所述处理器核心的架构状态。
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公开(公告)号：US10223204B2
公开(公告)日：2019-03-05
申请号：US13994609
申请日：2011-12-22
申请人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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公开(公告)号：US08275942B2
公开(公告)日：2012-09-25
申请号：US11316560
申请日：2005-12-22
CPC分类号： G06F12/0842
摘要： According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.
摘要翻译： 根据本发明的一个实施例，公开了一种用于选择高速缓存中的多个高速缓存路径的第一子集的方法，用于存储被识别为高优先级硬件线程的硬件线程，以用于与高速缓存通信的多线程处理器进行处理; 将高优先级的硬件线程分配给所选择的第一子集; 监视分配给所选择的多个高速缓存路线的第一子集的高优先级硬件线程的高速缓存使用; 以及如果所述高优先级硬件线程的高速缓存使用基于所述监视超过预定的非活动高速缓存使用阈值，则将所分配的高优先级硬件线程重新分配给所述多个高速缓存路径中的任何高速缓存方式。
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6.发明授权Method, apparatus, and a system for dynamically configuring a prefetcher based on a thread specific latency metric 有权方法，装置和用于基于线程特定的等待时间度量动态配置预取器的系统公开(公告)号：US08079031B2
公开(公告)日：2011-12-13
申请号：US11256536
申请日：2005-10-21
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/383 , G06F12/0862 , G06F2212/502
摘要： A discussion of a dynamic configuration for a prefetcher is proposed. For example, a thread specific latency metric is calculated and provides dynamic feedback to the software on a per thread basis via the configuration and status registers. Likewise, the software can optionally use the information from the registers to dynamically configure the prefetching behavior and allows the software to be able to both query the performance and configure the prefetcher.
摘要翻译： 提出了对预取器的动态配置的讨论。 例如，计算线程特定的延迟度量，并通过配置和状态寄存器在每个线程的基础上向软件提供动态反馈。 同样，软件可以选择使用来自寄存器的信息来动态地配置预取行为，并允许软件能够查询性能并配置预取器。
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7.发明申请GENERIC DEBUG EXTERNAL CONNECTION (GDXC) FOR HIGH INTEGRATION INTEGRATED CIRCUITS 有权用于高集成电路的通用调试外部连接（GDXC）公开(公告)号：US20100332927A1
公开(公告)日：2010-12-30
申请号：US12495583
申请日：2009-06-30
申请人： Tsvika Kurts , Guillermo Savransky , Jason Ratner , Eilon Hazan , Daniel Skaba , Sharon Elmosnino , Geeyarpuram N. Santhanakrishnan
发明人： Tsvika Kurts , Guillermo Savransky , Jason Ratner , Eilon Hazan , Daniel Skaba , Sharon Elmosnino , Geeyarpuram N. Santhanakrishnan
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31705 , G06F11/2236
摘要： A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.
摘要翻译： 高集成集成电路可以包括多个处理核心，图形处理单元，以及耦合到诸如环形结构的接口结构的无孔区域。 通用调试外部连接（GDXC）逻辑可以在环形结构的端点附近提供。 GDXC逻辑可以接收在环形结构内以及在多个核心和环形结构之间提供的接口上的非空间区域中发生的内部信号。 GDXC逻辑可以包括限定符，用于选择性地控制包括内部信号的信息的包的入口到队列中。 然后，GDXC逻辑可以将存储在队列中的分组传送到集成电路封装表面上提供的端口，以提供到分析工具的外部接口。
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8.发明授权Providing common caching agent for core and integrated input/output (IO) module 有权为核心和集成输入/输出（IO）模块提供通用缓存代理公开(公告)号：US08984228B2
公开(公告)日：2015-03-17
申请号：US13324053
申请日：2011-12-13
申请人： Yen-Cheng Liu , Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Kenneth C. Creta , Sridhar Muthrasanallur , Bahaa Fahim
发明人： Yen-Cheng Liu , Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Kenneth C. Creta , Sridhar Muthrasanallur , Bahaa Fahim
CPC分类号： G06F12/084 , G06F12/0815 , G06F12/0831 , G06F2212/452 , G06F2212/621 , Y02D10/13
摘要： In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有多个核心的多核处理器，共享高速缓存存储器，用于在多核处理器与耦合到多核处理器的至少一个IO设备之间进行接口的集成输入/输出（IIO）模块，以及 高速缓存代理以对多个核和IIO模块执行高速缓存一致性操作。 描述和要求保护其他实施例。
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9.发明授权Generic debug external connection (GDXC) for high integration integrated circuits 有权通用调试外部连接（GDXC）用于高集成度集成电路公开(公告)号：US08074131B2
公开(公告)日：2011-12-06
申请号：US12495583
申请日：2009-06-30
申请人： Tsvika Kurts , Guillermo Savransky , Jason Ratner , Eilon Hazan , Daniel Skaba , Sharon Elmosnino , Geeyarpuram N. Santhanakrishnan
发明人： Tsvika Kurts , Guillermo Savransky , Jason Ratner , Eilon Hazan , Daniel Skaba , Sharon Elmosnino , Geeyarpuram N. Santhanakrishnan
IPC分类号： G01R31/28
CPC分类号： G01R31/31705 , G06F11/2236
摘要： A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.
摘要翻译： 高集成集成电路可以包括多个处理核心，图形处理单元，以及耦合到诸如环形结构的接口结构的无孔区域。 通用调试外部连接（GDXC）逻辑可以在环形结构的端点附近提供。 GDXC逻辑可以接收在环形结构内以及在多个核心和环形结构之间提供的接口上的非空间区域中发生的内部信号。 GDXC逻辑可以包括限定符，用于选择性地控制包括内部信号的信息的包的入口到队列中。 然后，GDXC逻辑可以将存储在队列中的分组传送到集成电路封装表面上提供的端口，以提供到分析工具的外部接口。
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10.发明申请Opportunistic channel unblocking mechanism for ordered channels in a point-to-point interconnect 审中-公开点对点互连中有序通道的机会信道解锁机制公开(公告)号：US20080056230A1
公开(公告)日：2008-03-06
申请号：US11512878
申请日：2006-08-29
CPC分类号： H04L49/252
摘要： A system and method of opportunistically unblocking channels in an ordered channel architecture. Masking logic creates masking parameters based on partial addresses received with a message. A subsequent message is imparted with the masking parameters to determine if it should be blocked. Based on the result of the comparison, the message is placed in either a blocked buffer or an unblocked buffer so that messages in the unblocked buffer may make progress independent of the message in the blocked buffer.
摘要翻译： 一种有序通道架构中机会性解锁通道的系统和方法。 掩蔽逻辑基于使用消息接收的部分地址创建掩蔽参数。 向后续消息传递掩蔽参数以确定是否应该被阻止。 基于比较的结果，消息被放置在阻塞缓冲器或未阻塞缓冲器中，使得未阻塞缓冲器中的消息可以独立于阻塞缓冲器中的消息进行进展。
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