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    MULTI-VALUED LOGIC DEVICE HAVING NONVOLATILE MEMORY DEVICE
    13.
    发明申请
    MULTI-VALUED LOGIC DEVICE HAVING NONVOLATILE MEMORY DEVICE 有权
    具有非易失性存储器件的多值逻辑器件

    公开(公告)号：US20130121059A1

    公开(公告)日：2013-05-16

    申请号：US13564878

    申请日：2012-08-02

    申请人： Ho-jung Kim ,  Joong-ho Choi ,  Jai-kwang Shin ,  Hyun-sik Choi

    发明人： Ho-jung Kim ,  Joong-ho Choi ,  Jai-kwang Shin ,  Hyun-sik Choi

    IPC分类号： G11C11/00

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/30 ,  G11C16/34 ,  G11C16/3404

    摘要： A multi-valued logic device having an improved reliability includes a conversion unit configured to convert a multi level signal into a plurality of partial signals; and a plurality of nonvolatile memory devices configured to individually store the plurality of partial signals, wherein a number of bits of each of the plurality of partial signals individually stored in the plurality of nonvolatile memory devices is less than the number of bits of the multi level signal.

    摘要翻译： 具有改进的可靠性的多值逻辑器件包括被配置为将多电平信号转换成多个部分信号的转换单元; 以及多个非易失性存储器件，被配置为分别存储多个部分信号，其中分别存储在多个非易失性存储器件中的多个部分信号中的每一个的多个位都小于多级的位数 信号。

    Reconfigurable Logic Devices
    14.
    发明申请
    Reconfigurable Logic Devices 有权
    可重构逻辑器件

    公开(公告)号：US20120054417A1

    公开(公告)日：2012-03-01

    申请号：US13080938

    申请日：2011-04-06

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi

    IPC分类号： G06F12/02

    CPC分类号： H03K19/17752 ,  H03K19/17756

    摘要： Example embodiments provide a reconfigurable logic device including at least two logic blocks having a first logic block and a second logic block, a global wire group including at least a plurality of first global wires connected to the first logic block and a plurality of second global wires connected to the second logic block, and a global controller including a plurality of first nonvolatile memory devices associated with at least one first global wire and one second global wire, the global controller configured to selectively couple the pluralities of first and second global wires based on first data stored in the associated first nonvolatile memory devices.

    摘要翻译： 示例性实施例提供了一种可重新配置逻辑设备，其包括具有第一逻辑块和第二逻辑块的至少两个逻辑块，包括连接到第一逻辑块的至少多个第一全局线的全局线组和多个第二全局线 连接到第二逻辑块，以及全局控制器，其包括与至少一个第一全局线和一个第二全局线相关联的多个第一非易失性存储器件，所述全局控制器被配置为基于多个第一和第二全局线， 第一数据存储在相关的第一非易失性存储器件中。

    LOGIC DEVICE AND SEMICONDUCTOR PACKAGE HAVING THE SAME
    15.
    发明申请
    LOGIC DEVICE AND SEMICONDUCTOR PACKAGE HAVING THE SAME 有权
    具有相同功能的逻辑器件和半导体封装

    公开(公告)号：US20120326748A1

    公开(公告)日：2012-12-27

    申请号：US13494477

    申请日：2012-06-12

    申请人： Ho-jung Kim ,  Jae-kwang Shin ,  Hyun-sik Choi ,  Hyun-su Jeong

    发明人： Ho-jung Kim ,  Jae-kwang Shin ,  Hyun-sik Choi ,  Hyun-su Jeong

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

    摘要： According to example embodiments, a logic device includes a first functional block configured to perform a first operation according to first operation information and a second operation according to second operation information, and a second functional block configured to perform a third operation according to the first operation information and a fourth operation according to the second operation information. The first functional block is configured to receive configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the first or second operation based on the selected first or second operation information. The second functional block is configured to receive the configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the third or fourth operation based on the selected first or second operation information.

    摘要翻译： 根据示例性实施例，逻辑设备包括：第一功能块，被配置为根据第一操作信息执行第一操作，并且根据第二操作信息进行第二操作;以及第二功能块，被配置为根据第一操作执行第三操作 信息和根据第二操作信息的第四操作。 第一功能块被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作信息执行第一或第二操作。 第二功能块被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作信息来执行第三或第四操作。

    Real time reconfigurable logic device and semiconductor package having the same
    17.
    发明授权
    Real time reconfigurable logic device and semiconductor package having the same 有权
    具有相同功能的实时可重构逻辑器件和半导体封装

    公开(公告)号：US08754670B2

    公开(公告)日：2014-06-17

    申请号：US13494477

    申请日：2012-06-12

    申请人： Ho-jung Kim ,  Jae-kwang Shin ,  Hyun-sik Choi ,  Hyun-su Jeong

    发明人： Ho-jung Kim ,  Jae-kwang Shin ,  Hyun-sik Choi ,  Hyun-su Jeong

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

    摘要： According to example embodiments, a logic device includes a first functional block configured to perform a first operation according to first operation information and a second operation according to second operation information, and a second functional block configured to perform a third operation according to the first operation information and a fourth operation according to the second operation information. The first functional block is configured to receive configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the first or second operation based on the selected first or second operation information. The second functional block is configured to receive the configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the third or fourth operation based on the selected first or second operation information.

    摘要翻译： 根据示例性实施例，逻辑设备包括：第一功能块，被配置为根据第一操作信息执行第一操作，并且根据第二操作信息进行第二操作;以及第二功能块，被配置为根据第一操作执行第三操作 信息和根据第二操作信息的第四操作。 第一功能块被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作信息执行第一或第二操作。 第二功能块被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作信息来执行第三或第四操作。

    Reconfigurable logic devices
    18.
    发明授权
    Reconfigurable logic devices 有权
    可重构逻辑器件

    公开(公告)号：US08497703B2

    公开(公告)日：2013-07-30

    申请号：US13080938

    申请日：2011-04-06

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi

    IPC分类号： G06F7/38

    CPC分类号： H03K19/17752 ,  H03K19/17756

    摘要： Example embodiments provide a reconfigurable logic device including at least two logic blocks having a first logic block and a second logic block, a global wire group including at least a plurality of first global wires connected to the first logic block and a plurality of second global wires connected to the second logic block, and a global controller including a plurality of first nonvolatile memory devices associated with at least one first global wire and one second global wire, the global controller configured to selectively couple the pluralities of first and second global wires based on first data stored in the associated first nonvolatile memory devices.

    摘要翻译： 示例性实施例提供了一种可重新配置逻辑设备，其包括具有第一逻辑块和第二逻辑块的至少两个逻辑块，包括连接到第一逻辑块的至少多个第一全局线的全局线组和多个第二全局线 连接到第二逻辑块，以及全局控制器，其包括与至少一个第一全局线和一个第二全局线相关联的多个第一非易失性存储器件，所述全局控制器被配置为基于多个第一和第二全局线， 存储在相关联的第一非易失性存储器件中的第一数据。

    Resistor devices and digital-to-analog converters using the same
    19.
    发明授权
    Resistor devices and digital-to-analog converters using the same 有权
    电阻器件和使用相同的数模转换器

    公开(公告)号：US08477055B2

    公开(公告)日：2013-07-02

    申请号：US13157730

    申请日：2011-06-10

    申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

    发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

    IPC分类号： H03M1/66

    CPC分类号： H03M1/1061 ,  G11C13/0002 ,  H03M1/808

    摘要： A digital-to-analog converter (DAC) includes: a plurality of first controllers and a plurality of resistor devices. The plurality of first controllers are configured to be selectively switched on according to a received digital signal to control an analog signal according to the received digital signal. The plurality of resistor devices are respectively connected to the plurality of first controllers. The plurality of resistor devices include non-volatile memory devices.

    摘要翻译： 数模转换器（DAC）包括：多个第一控制器和多个电阻器件。 多个第一控制器被配置为根据所接收的数字信号选择性地接通，以根据所接收的数字信号来控制模拟信号。 多个电阻器件分别连接到多个第一控制器。 多个电阻器件包括非易失性存储器件。

    RESISTOR DEVICES AND DIGITAL-TO-ANALOG CONVERTERS USING THE SAME
    20.
    发明申请
    RESISTOR DEVICES AND DIGITAL-TO-ANALOG CONVERTERS USING THE SAME 有权
    使用相同的电阻器件和数字到模拟转换器

    公开(公告)号：US20120133538A1

    公开(公告)日：2012-05-31

    申请号：US13157730

    申请日：2011-06-10

    申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

    发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

    IPC分类号： H03M1/78

    CPC分类号： H03M1/1061 ,  G11C13/0002 ,  H03M1/808

    摘要： A digital-to-analog converter (DAC) includes: a plurality of first controllers and a plurality of resistor devices. The plurality of first controllers are configured to be selectively switched on according to a received digital signal to control an analog signal according to the received digital signal. The plurality of resistor devices are respectively connected to the plurality of first controllers. The plurality of resistor devices include non-volatile memory devices.

    摘要翻译： 数模转换器（DAC）包括：多个第一控制器和多个电阻器件。 多个第一控制器被配置为根据所接收的数字信号选择性地接通，以根据所接收的数字信号来控制模拟信号。 多个电阻器件分别连接到多个第一控制器。 多个电阻器件包括非易失性存储器件。