公开(公告)号：US08604827B2

公开(公告)日：2013-12-10

申请号：US13242060

申请日：2011-09-23

申请人： Hyung-su Jeong ,  Ho-jung Kim ,  Hyun-sik Choi

发明人： Hyung-su Jeong ,  Ho-jung Kim ,  Hyun-sik Choi

IPC分类号： H03K19/173

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  H03K19/1733

摘要： The logic circuit includes at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value. The selected value is selected from among a voltage and a current of an input signal, and the at least one variable resistance device is configured to memorize the resistance value. The logic circuit is configured to store multi-level data by setting the memorized resistance value.

摘要翻译： 逻辑电路包括至少一个可变电阻器件，其被配置为使得至少一个可变电阻器件的电阻值根据至少一个选定值而变化。 选择的值从输入信号的电压和电流中选择，并且至少一个可变电阻装置被配置为存储电阻值。 逻辑电路被配置为通过设置存储的电阻值来存储多电平数据。

公开(公告)号：US20120212255A1

公开(公告)日：2012-08-23

申请号：US13242060

申请日：2011-09-23

申请人： Hyung-su Jeong ,  Ho-jung Kim ,  Hyun-sik Choi

发明人： Hyung-su Jeong ,  Ho-jung Kim ,  Hyun-sik Choi

IPC分类号： H03K19/173 ,  G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  H03K19/1733

摘要： The logic circuit includes at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value. The selected value is selected from among a voltage and a current of an input signal, and the at least one variable resistance device is configured to memorize the resistance value. The logic circuit is configured to store multi-level data by setting the memorized resistance value.

摘要翻译： 逻辑电路包括至少一个可变电阻器件，其被配置为使得至少一个可变电阻器件的电阻值根据至少一个选定值而变化。 选择的值从输入信号的电压和电流中选择，并且至少一个可变电阻装置被配置为存储电阻值。 逻辑电路被配置为通过设置存储的电阻值来存储多电平数据。

公开(公告)号：US08963580B2

公开(公告)日：2015-02-24

申请号：US13597732

申请日：2012-08-29

申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Ki-chul Kim ,  Jai-kwang Shin ,  Joong-ho Choi ,  Hyung-su Jeong

发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Ki-chul Kim ,  Jai-kwang Shin ,  Joong-ho Choi ,  Hyung-su Jeong

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17756

摘要： A logic device may include a first functional block, the first functional block including, a first storage block, a second storage block, and a first function controller. In a first operation time period, the first function controller may be configured to receive a first configuration selection signal and a first configuration command signal that instructs a first function be configured, select the first storage block as a configured storage block in the first operation time period based on the first configuration selection signal, and configure the first function in the first storage block based on the first configuration command signal.

摘要翻译： 逻辑设备可以包括第一功能块，第一功能块包括第一存储块，第二存储块和第一功能控制器。 在第一操作时间段中，第一功能控制器可以被配置为接收第一配置选择信号和指示第一功能的第一配置命令信号，在第一操作时间中选择第一存储块作为配置的存储块 基于第一配置选择信号，并且基于第一配置命令信号来配置第一存储块中的第一功能。

公开(公告)号：US08503220B2

公开(公告)日：2013-08-06

申请号：US13233304

申请日：2011-09-15

申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi ,  Hyung-su Jeong

发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi ,  Hyung-su Jeong

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C7/04 ,  G11C7/062 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0016 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/004 ,  G11C2207/002

摘要： In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The sensing unit includes a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit.

摘要翻译： 在一个示例性实施例中，半导体器件包括存储单元阵列，其具有设置在至少一个位线和至少一个字线交叉的区域中的至少一个存储单元。 感测单元感测存储在至少一个存储单元中的数据。 感测单元包括连接控制单元，其被配置为基于控制信号来控制至少一个位线和感测线之间的连接，所述控制信号具有基于由感测感测的数据的值而变化的电压电平 单元。

公开(公告)号：US20120140545A1

公开(公告)日：2012-06-07

申请号：US13233304

申请日：2011-09-15

申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi ,  Hyung-su Jeong

发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi ,  Hyung-su Jeong

IPC分类号： G11C11/00 ,  G11C7/12 ,  G11C7/00 ,  G11C7/06

CPC分类号： G11C7/12 ,  G11C7/04 ,  G11C7/062 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0016 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/004 ,  G11C2207/002

摘要： In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The sensing unit includes a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit.

摘要翻译： 在一个示例性实施例中，半导体器件包括存储单元阵列，其具有设置在至少一个位线和至少一个字线交叉的区域中的至少一个存储单元。 感测单元感测存储在至少一个存储单元中的数据。 感测单元包括连接控制单元，其被配置为基于控制信号来控制至少一个位线和感测线之间的连接，所述控制信号具有基于由感测感测的数据的值而变化的电压电平 单元。

公开(公告)号：US08477055B2

公开(公告)日：2013-07-02

申请号：US13157730

申请日：2011-06-10

申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

IPC分类号： H03M1/66

CPC分类号： H03M1/1061 ,  G11C13/0002 ,  H03M1/808

摘要： A digital-to-analog converter (DAC) includes: a plurality of first controllers and a plurality of resistor devices. The plurality of first controllers are configured to be selectively switched on according to a received digital signal to control an analog signal according to the received digital signal. The plurality of resistor devices are respectively connected to the plurality of first controllers. The plurality of resistor devices include non-volatile memory devices.

摘要翻译： 数模转换器（DAC）包括：多个第一控制器和多个电阻器件。 多个第一控制器被配置为根据所接收的数字信号选择性地接通，以根据所接收的数字信号来控制模拟信号。 多个电阻器件分别连接到多个第一控制器。 多个电阻器件包括非易失性存储器件。

公开(公告)号：US20120133538A1

公开(公告)日：2012-05-31

申请号：US13157730

申请日：2011-06-10

申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

IPC分类号： H03M1/78

CPC分类号： H03M1/1061 ,  G11C13/0002 ,  H03M1/808

摘要： A digital-to-analog converter (DAC) includes: a plurality of first controllers and a plurality of resistor devices. The plurality of first controllers are configured to be selectively switched on according to a received digital signal to control an analog signal according to the received digital signal. The plurality of resistor devices are respectively connected to the plurality of first controllers. The plurality of resistor devices include non-volatile memory devices.

摘要翻译： 数模转换器（DAC）包括：多个第一控制器和多个电阻器件。 多个第一控制器被配置为根据所接收的数字信号选择性地接通，以根据所接收的数字信号来控制模拟信号。 多个电阻器件分别连接到多个第一控制器。 多个电阻器件包括非易失性存储器件。

公开(公告)号：US08471640B2

公开(公告)日：2013-06-25

申请号：US13064627

申请日：2011-04-05

申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Jai-kwang Shin

发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Jai-kwang Shin

IPC分类号： H03B17/00

CPC分类号： H03B15/006

摘要： Oscillators and methods of operating the oscillators are provided, the oscillators include an oscillating unit including at least one magnetic layer having a magnetization direction that varies according to at least one selected from the group consisting of an applied current, an applied voltage and an applied magnetic field. The oscillating unit is configured to generate an oscillation signal having a set frequency. The oscillators further include an output stage that provides an output signal by differentially amplifying the oscillation signal.

摘要翻译： 提供振荡器和操作振荡器的方法，振荡器包括振荡单元，该振荡单元包括至少一个具有磁化方向的磁性层，磁化方向根据从施加的电流，施加的电压和施加的磁体中选择的至少一个而变化 领域。 振荡单元被配置为产生具有设定频率的振荡信号。 振荡器还包括通过差分放大振荡信号来提供输出信号的输出级。

公开(公告)号：US20120112796A1

公开(公告)日：2012-05-10

申请号：US13064627

申请日：2011-04-05

申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Jai-kwang Shin

发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Jai-kwang Shin

IPC分类号： H03K5/01

CPC分类号： H03B15/006

摘要： Oscillators and methods of operating the oscillators are provided, the oscillators include an oscillating unit including at least one magnetic layer having a magnetization direction that varies according to at least one selected from the group consisting of an applied current, an applied voltage and an applied magnetic field. The oscillating unit is configured to generate an oscillation signal having a set frequency. The oscillators further include an output stage that provides an output signal by differentially amplifying the oscillation signal.

摘要翻译： 提供振荡器和操作振荡器的方法，振荡器包括振荡单元，该振荡单元包括至少一个具有磁化方向的磁性层，磁化方向根据从施加的电流，施加的电压和施加的磁体中选择的至少一个而变化 领域。 振荡单元被配置为产生具有设定频率的振荡信号。 振荡器还包括通过差分放大振荡信号来提供输出信号的输出级。

公开(公告)号：US08861268B2

公开(公告)日：2014-10-14

申请号：US13564878

申请日：2012-08-02

申请人： Ho-jung Kim ,  Joong-ho Choi ,  Jai-kwang Shin ,  Hyun-sik Choi

发明人： Ho-jung Kim ,  Joong-ho Choi ,  Jai-kwang Shin ,  Hyun-sik Choi

IPC分类号： G11C16/12 ,  G11C16/30 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/30 ,  G11C16/34 ,  G11C16/3404

摘要： A multi-valued logic device having an improved reliability includes a conversion unit configured to convert a multi level signal into a plurality of partial signals; and a plurality of nonvolatile memory devices configured to individually store the plurality of partial signals, wherein a number of bits of each of the plurality of partial signals individually stored in the plurality of nonvolatile memory devices is less than the number of bits of the multi level signal.

摘要翻译： 具有改进的可靠性的多值逻辑器件包括被配置为将多电平信号转换成多个部分信号的转换单元; 以及多个非易失性存储器件，被配置为分别存储多个部分信号，其中分别存储在多个非易失性存储器件中的多个部分信号中的每一个的多个位都小于多级的位数 信号。