公开(公告)号：US08477055B2

公开(公告)日：2013-07-02

申请号：US13157730

申请日：2011-06-10

申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

IPC分类号： H03M1/66

CPC分类号： H03M1/1061 ,  G11C13/0002 ,  H03M1/808

摘要： A digital-to-analog converter (DAC) includes: a plurality of first controllers and a plurality of resistor devices. The plurality of first controllers are configured to be selectively switched on according to a received digital signal to control an analog signal according to the received digital signal. The plurality of resistor devices are respectively connected to the plurality of first controllers. The plurality of resistor devices include non-volatile memory devices.

摘要翻译： 数模转换器（DAC）包括：多个第一控制器和多个电阻器件。 多个第一控制器被配置为根据所接收的数字信号选择性地接通，以根据所接收的数字信号来控制模拟信号。 多个电阻器件分别连接到多个第一控制器。 多个电阻器件包括非易失性存储器件。

公开(公告)号：US20120133538A1

公开(公告)日：2012-05-31

申请号：US13157730

申请日：2011-06-10

申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Hyung-su Jeong

IPC分类号： H03M1/78

CPC分类号： H03M1/1061 ,  G11C13/0002 ,  H03M1/808

摘要： A digital-to-analog converter (DAC) includes: a plurality of first controllers and a plurality of resistor devices. The plurality of first controllers are configured to be selectively switched on according to a received digital signal to control an analog signal according to the received digital signal. The plurality of resistor devices are respectively connected to the plurality of first controllers. The plurality of resistor devices include non-volatile memory devices.

摘要翻译： 数模转换器（DAC）包括：多个第一控制器和多个电阻器件。 多个第一控制器被配置为根据所接收的数字信号选择性地接通，以根据所接收的数字信号来控制模拟信号。 多个电阻器件分别连接到多个第一控制器。 多个电阻器件包括非易失性存储器件。

公开(公告)号：US20120212255A1

公开(公告)日：2012-08-23

申请号：US13242060

申请日：2011-09-23

申请人： Hyung-su Jeong ,  Ho-jung Kim ,  Hyun-sik Choi

发明人： Hyung-su Jeong ,  Ho-jung Kim ,  Hyun-sik Choi

IPC分类号： H03K19/173 ,  G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  H03K19/1733

摘要： The logic circuit includes at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value. The selected value is selected from among a voltage and a current of an input signal, and the at least one variable resistance device is configured to memorize the resistance value. The logic circuit is configured to store multi-level data by setting the memorized resistance value.

摘要翻译： 逻辑电路包括至少一个可变电阻器件，其被配置为使得至少一个可变电阻器件的电阻值根据至少一个选定值而变化。 选择的值从输入信号的电压和电流中选择，并且至少一个可变电阻装置被配置为存储电阻值。 逻辑电路被配置为通过设置存储的电阻值来存储多电平数据。

公开(公告)号：US08963580B2

公开(公告)日：2015-02-24

申请号：US13597732

申请日：2012-08-29

申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Ki-chul Kim ,  Jai-kwang Shin ,  Joong-ho Choi ,  Hyung-su Jeong

发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Ki-chul Kim ,  Jai-kwang Shin ,  Joong-ho Choi ,  Hyung-su Jeong

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17756

摘要： A logic device may include a first functional block, the first functional block including, a first storage block, a second storage block, and a first function controller. In a first operation time period, the first function controller may be configured to receive a first configuration selection signal and a first configuration command signal that instructs a first function be configured, select the first storage block as a configured storage block in the first operation time period based on the first configuration selection signal, and configure the first function in the first storage block based on the first configuration command signal.

摘要翻译： 逻辑设备可以包括第一功能块，第一功能块包括第一存储块，第二存储块和第一功能控制器。 在第一操作时间段中，第一功能控制器可以被配置为接收第一配置选择信号和指示第一功能的第一配置命令信号，在第一操作时间中选择第一存储块作为配置的存储块 基于第一配置选择信号，并且基于第一配置命令信号来配置第一存储块中的第一功能。

公开(公告)号：US08503220B2

公开(公告)日：2013-08-06

申请号：US13233304

申请日：2011-09-15

申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi ,  Hyung-su Jeong

发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi ,  Hyung-su Jeong

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C7/04 ,  G11C7/062 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0016 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/004 ,  G11C2207/002

摘要： In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The sensing unit includes a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit.

摘要翻译： 在一个示例性实施例中，半导体器件包括存储单元阵列，其具有设置在至少一个位线和至少一个字线交叉的区域中的至少一个存储单元。 感测单元感测存储在至少一个存储单元中的数据。 感测单元包括连接控制单元，其被配置为基于控制信号来控制至少一个位线和感测线之间的连接，所述控制信号具有基于由感测感测的数据的值而变化的电压电平 单元。

公开(公告)号：US20120140545A1

公开(公告)日：2012-06-07

申请号：US13233304

申请日：2011-09-15

申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi ,  Hyung-su Jeong

发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi ,  Hyung-su Jeong

IPC分类号： G11C11/00 ,  G11C7/12 ,  G11C7/00 ,  G11C7/06

CPC分类号： G11C7/12 ,  G11C7/04 ,  G11C7/062 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0016 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/004 ,  G11C2207/002

摘要： In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The sensing unit includes a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit.

摘要翻译： 在一个示例性实施例中，半导体器件包括存储单元阵列，其具有设置在至少一个位线和至少一个字线交叉的区域中的至少一个存储单元。 感测单元感测存储在至少一个存储单元中的数据。 感测单元包括连接控制单元，其被配置为基于控制信号来控制至少一个位线和感测线之间的连接，所述控制信号具有基于由感测感测的数据的值而变化的电压电平 单元。

公开(公告)号：US08604827B2

公开(公告)日：2013-12-10

申请号：US13242060

申请日：2011-09-23

申请人： Hyung-su Jeong ,  Ho-jung Kim ,  Hyun-sik Choi

发明人： Hyung-su Jeong ,  Ho-jung Kim ,  Hyun-sik Choi

IPC分类号： H03K19/173

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  H03K19/1733

摘要： The logic circuit includes at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value. The selected value is selected from among a voltage and a current of an input signal, and the at least one variable resistance device is configured to memorize the resistance value. The logic circuit is configured to store multi-level data by setting the memorized resistance value.

摘要翻译： 逻辑电路包括至少一个可变电阻器件，其被配置为使得至少一个可变电阻器件的电阻值根据至少一个选定值而变化。 选择的值从输入信号的电压和电流中选择，并且至少一个可变电阻装置被配置为存储电阻值。 逻辑电路被配置为通过设置存储的电阻值来存储多电平数据。

公开(公告)号：US08003419B2

公开(公告)日：2011-08-23

申请号：US12458900

申请日：2009-07-27

申请人： Kyoung-kook Kim ,  Su-hee Chae ,  Young-soo Park ,  Taek Kim ,  Moon-seung Yang ,  Hyung-su Jeong ,  Jae-chul Park ,  Jun-youn Kim

发明人： Kyoung-kook Kim ,  Su-hee Chae ,  Young-soo Park ,  Taek Kim ,  Moon-seung Yang ,  Hyung-su Jeong ,  Jae-chul Park ,  Jun-youn Kim

IPC分类号： H01L21/00

CPC分类号： H01L33/0079 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a method of manufacturing a light emitting device from a large-area bonding wafer by using a wafer bonding method using. The method may include forming a plurality of semiconductor layers, each having an active region for emitting light, on a plurality of growth substrates. The method may also include arranging the plurality of growth substrates on which the semiconductor layers are formed on one bonding substrate and simultaneously processing each of the semiconductor layers formed on each of the growth substrates through subsequent processes. The bonding wafer may be formed of a material that reduces or prevents bending or warping due to a difference of thermal expansion coefficients between a wafer material, such as sapphire, and a bonding wafer. According to the above method, because a plurality of wafers may be processed by one process, mass production of LEDs may be possible which may reduce manufacturing costs.

摘要翻译： 提供了一种使用晶片接合方法从大面积接合晶片制造发光器件的方法。 该方法可以包括在多个生长衬底上形成多个半导体层，每个半导体层具有发射光的有源区。 该方法还可以包括在其上形成半导体层的多个生长衬底布置在一个接合衬底上，并且通过后续处理同时处理在每个生长衬底上形成的每个半导体层。 接合晶片可以由减少或防止由于晶片材料（例如蓝宝石）和接合晶片之间的热膨胀系数的差异而导致的弯曲或翘曲的材料形成。 根据上述方法，由于可以通过一个处理来处理多个晶片，因此大量生产LED可能会降低制造成本。

公开(公告)号：US20110127554A1

公开(公告)日：2011-06-02

申请号：US12801198

申请日：2010-05-27

申请人： Jae-won Lee ,  Bok-ki Min ,  Jun-youn Kim ,  Young-jo Tak ,  Hyung-su Jeong

发明人： Jae-won Lee ,  Bok-ki Min ,  Jun-youn Kim ,  Young-jo Tak ,  Hyung-su Jeong

IPC分类号： H01L33/46 ,  H01L33/00

CPC分类号： H01L33/60 ,  H01L33/007 ,  H01L33/10 ,  H01L33/382 ,  H01L33/387 ,  H01L33/405 ,  H01L33/46 ,  H01L2933/0016

摘要： A light emitting device may include a substrate, an n-type clad layer, an active layer, and a p-type clad layer. A concave-convex pattern having a plurality of grooves and a mesa between each of the plurality of grooves may be formed on the substrate, and a reflective layer may be formed on the surfaces of the plurality of grooves or the mesa between each of the plurality of grooves. Therefore, light generated in the active layer may be reflected by the reflective layer, and extracted to an external location.

摘要翻译： 发光器件可以包括衬底，n型覆盖层，有源层和p型覆盖层。 可以在基板上形成具有多个凹槽和每个凹槽之间的台面的凹凸图案，并且可以在多个凹槽或多个凹槽中的每一个之间的台面的表面上形成反射层 的凹槽。 因此，有源层中产生的光可以被反射层反射，并被提取到外部位置。

公开(公告)号：US20130200427A1

公开(公告)日：2013-08-08

申请号：US13550032

申请日：2012-07-16

申请人： Hyung-su Jeong ,  Jai-kwang Shin ,  Nam-young Lee ,  Ji-hoon Lee ,  Min-kwon Cho ,  Yong-cheol Choi ,  Hyuk-soon Choi

发明人： Hyung-su Jeong ,  Jai-kwang Shin ,  Nam-young Lee ,  Ji-hoon Lee ,  Min-kwon Cho ,  Yong-cheol Choi ,  Hyuk-soon Choi

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L29/36 ,  H01L29/6634 ,  H01L29/7397

摘要： A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution.

摘要翻译： 晶体管包括器件部分和集电极层。 器件部分位于半导体衬底的第一侧，并且包括栅极和发射极。 集电极层位于半导体衬底的与第一侧相对的第二侧上。 集电极层是杂质掺杂的外延层，并具有非正态分布的掺杂分布。