公开(公告)号：US08987144B2

公开(公告)日：2015-03-24

申请号：US13198107

申请日：2011-08-04

申请人： Stephan Kronholz ,  Markus Lenski ,  Hans-Juergen Thees

发明人： Stephan Kronholz ,  Markus Lenski ,  Hans-Juergen Thees

IPC分类号： H01L21/302 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115

CPC分类号： H01L21/823864 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.

摘要翻译： 在复杂的半导体器件中，高k金属栅极电极结构可以在早期制造阶段形成，其中敏感栅极材料的完整性通过在选定的活性区域中选择性沉积应变诱导半导体材料之后提供附加的衬垫材料。 此外，可以基于通过避免图案化和去除任何牺牲氧化物间隔物而显着降低隔离区域和有源区域中的材料侵蚀程度的工艺流程来去除栅电极结构的电介质盖材料。

公开(公告)号：US08835298B2

公开(公告)日：2014-09-16

申请号：US13415492

申请日：2012-03-08

申请人： Sivakumar Kumarasamy ,  Clemens Fitz ,  Markus Lenski ,  Jochen Poth ,  Kristin Schupke

发明人： Sivakumar Kumarasamy ,  Clemens Fitz ,  Markus Lenski ,  Jochen Poth ,  Kristin Schupke

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28518 ,  H01L22/12 ,  H01L22/20

摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni′/Pt layer at a temperature of 130° C.

摘要翻译： 如果检测到Pt残留物，则通过执行包括在SWC工具中在130℃的温度下施加SPM的返工来减少形成含Pt的NiSi后剩余的Pt残余物的量。 实施例包括在半导体衬底上沉积一层Ni / Pt，退火沉积的Ni / Pt层，从退火的Ni / Pt层去除未反应的Ni，退火Ni去除的Ni / Pt层，从退火的Ni中除去未反应的Pt Ni / Pt层，分析未去除Pt残留物的Pt去除Ni / Pt层，如果检测到未反应的Pt残留物，则在SWC工具中将Pt施加到去除的Pt / Ni层上。 可以在130℃的温度下将SPM施加到Pt去除的Ni'/ Pt层上

公开(公告)号：US08765559B2

公开(公告)日：2014-07-01

申请号：US13358101

申请日：2012-01-25

申请人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski ,  Frank Seliger ,  Frank Richter

发明人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski ,  Frank Seliger ,  Frank Richter

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： When forming sophisticated gate electrode structures, such as high-k metal gate electrode structures, an appropriate encapsulation may be achieved, while also undue material loss of a strain-inducing semiconductor material that is provided in one type of transistor may be avoided. To this end, the patterning of the protective spacer structure prior to depositing the strain-inducing semiconductor material may be achieved for each type of transistor on the basis of the same process flow, while, after the deposition of the strain-inducing semiconductor material, an etch stop layer may be provided so as to preserve integrity of the active regions.

摘要翻译： 当形成诸如高k金属栅电极结构的复杂的栅电极结构时，可以实现适当的封装，同时也可以避免在一种晶体管中提供的应变诱导半导体材料的不适当的材料损耗。 为此，可以在沉积应变诱导半导体材料之前对保护间隔物结构进行图案化，其基于相同的工艺流程，对于每种类型的晶体管，在应变诱导半导体材料沉积之后， 可以提供蚀刻停止层，以便保持活性区域的完整性。

公开(公告)号：US08557667B2

公开(公告)日：2013-10-15

申请号：US10987484

申请日：2004-11-12

申请人： Hartmut Rülke ,  Katja Huy ,  Markus Lenski

发明人： Hartmut Rülke ,  Katja Huy ,  Markus Lenski

IPC分类号： H01L21/336

CPC分类号： H01L22/10 ,  H01L21/3185 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer elements that modify the charge carrier mobility and thus the conductivity of the channel region of a field effect transistor.

摘要翻译： 通过降低沉积速率并保持等离子体气氛中的低偏压功率，可以沉积显示拉伸应力的间隔层，例如氮化硅层。 拉伸应力的量在宽范围内是可控的，从而提供形成改变电场载流子迁移率并因此改变场效应晶体管的沟道区的导电性的侧壁间隔元件的潜力。

公开(公告)号：US08383500B2

公开(公告)日：2013-02-26

申请号：US12914234

申请日：2010-10-28

申请人： Gerd Marxsen ,  Joachim Metzger ,  Robert Binder ,  Markus Lenski

发明人： Gerd Marxsen ,  Joachim Metzger ,  Robert Binder ,  Markus Lenski

IPC分类号： H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： In a replacement gate approach, one work function metal may be provided in an early manufacturing stage, i.e., upon depositing the gate layer stack, thereby reducing the number of deposition steps required in a later manufacturing stage. Consequently, the further work function metal and the electrode metal may be filled into the gate trenches on the basis of superior process conditions compared to conventional replacement gate approaches.

摘要翻译： 在替代栅极方法中，可以在早期制造阶段（即，在沉积栅极层堆叠时）提供一个功函数金属，从而减少后续制造阶段所需的沉积步骤的数量。 因此，与传统的替代栅极方法相比，基于优越的工艺条件，可以将另外的功函数金属和电极金属填充到栅极沟槽中。

公开(公告)号：US08357573B2

公开(公告)日：2013-01-22

申请号：US12772436

申请日：2010-05-03

申请人： Stephan Kronholz ,  Markus Lenski ,  Vassilios Papageorgiou

发明人： Stephan Kronholz ,  Markus Lenski ,  Vassilios Papageorgiou

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51

摘要： Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.

摘要翻译： 基于嵌入式应变诱发半导体合金，可以通过基于高k介电材料与含金属盖层组合形成栅电极结构来增强P沟道晶体管的性能，以获得 栅电极结构的底切配置。 因此，应变诱导半导体合金可以基于最小厚度的侧壁间隔物形成，以便使应变诱导半导体材料更靠近沟道区的中心区域。

公开(公告)号：US08349694B2

公开(公告)日：2013-01-08

申请号：US12909149

申请日：2010-10-21

申请人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Martin Gerhardt

发明人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Martin Gerhardt

IPC分类号： H01L21/28 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal.

摘要翻译： 当在复杂的半导体器件的一种类型的晶体管中形成应变诱导半导体合金时，可以通过在每个栅极电极结构上形成封装间隔元件并提供额外的硬度来实现栅电极结构的电介质盖材料的优良厚度均匀性 面具材料。 因此，特别地，在复杂的替代栅极方法中，可以在稍后的制造阶段中有效地去除电介质盖材料，从而避免在用电极金属替换半导体材料时的任何不规则性。

公开(公告)号：US07981740B2

公开(公告)日：2011-07-19

申请号：US12821583

申请日：2010-06-23

申请人： Markus Lenski ,  Kerstin Ruttloff ,  Martin Mazur ,  Frank Seliger ,  Ralf Otterbach

发明人： Markus Lenski ,  Kerstin Ruttloff ,  Martin Mazur ,  Frank Seliger ,  Ralf Otterbach

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

摘要： When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.

摘要翻译： 当在复杂的高k金属栅极结构的基础上形成晶体管元件时，可以通过更有效地调节不同导电类型的晶体管的栅极高度来增强置换栅极方法的效率，当晶体管的介质盖层可能经历了 因此可能需要在一种类型的晶体管中随后适应最终的盖层厚度。 为此，可以在用于在一个栅电极结构中形成偏移间隔元件同时覆盖另一栅电极结构的处理顺序期间使用硬掩模材料。

公开(公告)号：US20100221906A1

公开(公告)日：2010-09-02

申请号：US12711481

申请日：2010-02-24

申请人： Joachim Metzger ,  Robert Binder ,  Markus Lenski ,  Klaus Hempel

发明人： Joachim Metzger ,  Robert Binder ,  Markus Lenski ,  Klaus Hempel

IPC分类号： H01L21/28

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66772

摘要： During a manufacturing sequence for forming a sophisticated high-k metal gate structure, a cover layer, such as a silicon layer, may be deposited on a metal cap layer in an in situ process in order to enhance integrity of the metal cap layer. The cover layer may provide superior integrity during the further processing, for instance in view of performing wet chemical cleaning processes and the subsequent deposition of a silicon gate material.

摘要翻译： 在用于形成复杂的高k金属栅极结构的制造顺序期间，覆盖层（例如硅层）可以在原位工艺中沉积在金属覆盖层上，以便提高金属覆盖层的完整性。 覆盖层可以在进一步加工期间提供优异的完整性，例如考虑到执行湿化学清洗工艺和随后沉积硅栅材料。

公开(公告)号：US20090286389A1

公开(公告)日：2009-11-19

申请号：US12122840

申请日：2008-05-19

申请人： David G. Farber ,  Fred Hause ,  Markus Lenski ,  Anthony C. Mowry

发明人： David G. Farber ,  Fred Hause ,  Markus Lenski ,  Anthony C. Mowry

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L29/6653 ,  H01L29/78

摘要： A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.

摘要翻译： 一种方法，包括在衬底上形成半导体器件的栅极，并且蚀刻栅极侧面上的侧壁间隔物以提供接近值，其中接近值被定义为栅极与性能增强的边缘之间的距离 地区。 侧壁间隔件用于在衬底中形成区域期间限定区域的边缘。 该方法还包括预先清洁栅极和基板以准备形成区域，其中在连续真空中进行蚀刻和预清洁。