-
公开(公告)号：US20180150090A1
公开(公告)日：2018-05-31
申请号：US15494329
申请日：2017-04-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-An CHANG , Chia-Fu LEE , YU-DER CHIH , Yi-Chun SHIH
IPC: G05F1/56
CPC classification number: G05F1/56
Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
-
公开(公告)号：US20150109850A1
公开(公告)日：2015-04-23
申请号：US14061539
申请日：2013-10-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yang CHANG , Chia-Fu LEE , Wen-Ting CHU , Yue-Der CHIH
CPC classification number: G11C13/0026 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/009 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/16
Abstract: A device is disclosed that includes an I/O memory block. The I/O memory block includes memory cells, bit lines and a source line. The number of the formed bit lines is at least 4. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.
Abstract translation: 公开了一种包括I / O存储器块的装置。 I / O存储器块包括存储单元，位线和源极线。 所形成的位线的数量至少为4.位线和源极线电连接到存储器单元。 在I / O存储器块中，源线和位线被配置为向存储器单元提供逻辑数据。
-
公开(公告)号：US20220115051A1
公开(公告)日：2022-04-14
申请号：US17559998
申请日：2021-12-22
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chia-Fu LEE , Yu-Der CHIH , Hon-Jarn LIN , Yi-Chun SHIH
Abstract: A device includes first and second reference storage units, and first and second reference switches. The first reference switch outputs a first current at a first terminal thereof to the first reference storage unit. The first reference storage unit receives the first current at a first terminal thereof and generates a first signal, according to the first current, at a second terminal thereof to an average current circuit. The second reference switch outputs a second current at a first terminal thereof to the second reference storage unit. The second reference storage unit receives the second current at a first terminal thereof, and generates a second signal, according to the second current, at a second terminal thereof to the average current circuit. The first and second reference switches are coupled to a plurality of first memory cells by a first word line.
-
Patent Agency Ranking
公开(公告)号：US20210294368A1
公开(公告)日：2021-09-23
申请号：US17339818
申请日：2021-06-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-An CHANG , Chia-Fu LEE , Yu-Der CHIH , Yi-Chun SHIH
IPC: G05F1/56
Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
-
公开(公告)号：US20200150703A1
公开(公告)日：2020-05-14
申请号：US16738963
申请日：2020-01-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-An CHANG , Chia-Fu LEE , Yu-Der CHIH , Yi-Chun SHIH
IPC: G05F1/56
Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
-
公开(公告)号：US20170125071A1
公开(公告)日：2017-05-04
申请号：US14929076
申请日：2015-10-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chia-Fu LEE , Yu-Der CHIH , Hon-Jarn LIN , Yi-Chun SHIH
CPC classification number: G11C11/1673 , G11C7/062 , G11C7/22 , G11C11/161 , G11C13/004 , G11C2013/0045 , G11C2013/0054 , G11C2013/0057 , G11C2207/063
Abstract: A device is disclosed that includes memory cells, a reference circuit, and a sensing unit. Each of the memory cells is configured to store bit data. The reference circuit includes reference switches and reference storage units. The reference switches are disposed. A first reference storage unit of the reference storage units is configured to generate a first signal having a first logic state when a first reference switch the reference switches is turned on. A second reference storage unit of the reference storage units is configured to generate a second signal having a second logic state when a second reference switch of the reference switches is turned on. The sensing unit is configured to determine a logic state of the bit data of one of the memory cells according to the first signal and the second signal.
-
公开(公告)号：US20140003141A1
公开(公告)日：2014-01-02
申请号：US14014471
申请日：2013-08-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tien-Chun YANG , Chia-Fu LEE , Yue-Der CHIH
IPC: G11C16/06
CPC classification number: G11C16/06 , G11C16/30 , G11C2216/22
Abstract: A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.
Abstract translation: 设备包括地址存储设备。 第一电路包括第一闪存，其被配置为顺序地接收第一和第二地址并将第一地址存储在地址存储设备中。 第一电路具有第一组控制输入，用于使第一电路从与第一和第二地址中所选择的一个对应的第一闪存的单元上的读取，编程和擦除组合执行第一操作。 第二电路包括被配置为接收第二地址的第二闪存。 第二电路具有第二组控制输入，用于在执行第一操作时使第二电路从对应于第二地址的第二闪速存储器的单元读取数据。
-
公开(公告)号：US20130064017A1
公开(公告)日：2013-03-14
申请号：US13670607
申请日：2012-11-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tien-Chun YANG , Chia-Fu LEE , Yue-Der CHIH
CPC classification number: G11C16/06 , G11C16/30 , G11C2216/22
Abstract: A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.
Abstract translation: 设备包括地址存储设备。 第一电路包括第一闪存，其被配置为顺序地接收第一和第二地址并将第一地址存储在地址存储设备中。 第一电路具有第一组控制输入，用于使第一电路从与第一和第二地址中的所选择的一个对应的第一闪存的单元上的读取，编程和擦除组合执行第一操作。 第二电路包括被配置为接收第二地址的第二闪存。 第二电路具有第二组控制输入，用于在执行第一操作时使第二电路从对应于第二地址的第二闪速存储器的单元读取数据。
-
-
-
-
-
-
-
Search Results
18
records
(took 0.017 seconds)
