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    PHASE SHIFTER CIRCUIT, PHASE SHIFTER LAYOUT AND METHOD OF FORMING THE SAME
    11.
    发明申请
    PHASE SHIFTER CIRCUIT, PHASE SHIFTER LAYOUT AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20220300694A1

    公开(公告)日：2022-09-22

    申请号：US17833436

    申请日：2022-06-06

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chi-Hsien LIN ,  Ho-Hsiang CHEN ,  Hsien-Yuan LIAO ,  Tzu-Jin YEH ,  Ying-Ta LU

    IPC: G06F30/398 ,  G03F1/70 ,  G03F1/36

    Abstract: A phase shifter includes a first transistor and a second transistor. The first transistor includes a first gate terminal configured to receive a first voltage. The first transistor is configured to adjust at least a resistance or a first capacitance of the phase shifter responsive to the first voltage. The second transistor is coupled to the first transistor. The second transistor includes a second gate terminal configured to receive a second voltage. The second transistor is configured to adjust a second capacitance of the phase shifter responsive to the second voltage. The second gate terminal includes a first polysilicon portion and a second polysilicon portion extending in a first direction. The first polysilicon portion and the second polysilicon portion are positioned along opposite edges of an active region of the first transistor and the second transistor.

    DIFFERENTIAL OSCILLATOR CIRCUIT
    12.
    发明申请
    DIFFERENTIAL OSCILLATOR CIRCUIT 有权

    公开(公告)号：US20220255504A1

    公开(公告)日：2022-08-11

    申请号：US17732400

    申请日：2022-04-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chi-Hsien LIN ,  Ho-Hsiang CHEN ,  Hsien-Yuan LIAO ,  Tzu-Jin YEH ,  Ying-Ta LU

    IPC: H03B5/12 ,  H03B1/04 ,  H03H7/01

    Abstract: A differential oscillator includes a differential circuit and a transformer-coupled band-pass filter (BPF) coupled between first and second output nodes. The BPF includes a coupling device coupled between the output nodes and a transformer including first and second windings in a metal layer of an IC. The first winding includes first and second conductive structures coupled to the first output node and a voltage node, respectively, and a third conductive structure including first and second extending portions connected to the first and second conductive structures, respectively. The second winding includes a fourth conductive structure including a third extending portion coupled to the voltage node and a fourth extending portion coupled to the second output node. The third extending portion is between the second conductive structure and the first extending portion, and the fourth extending portion is between the first conductive structure and the second extending portion.

    INTEGRATED CIRCUIT WITH GUARD RING
    18.
    发明申请
    INTEGRATED CIRCUIT WITH GUARD RING 有权

    公开(公告)号：US20210358844A1

    公开(公告)日：2021-11-18

    申请号：US17389795

    申请日：2021-07-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chiao-Han LEE ,  Chi-Hsien LIN ,  Ho-Hsiang CHEN ,  Hsien-Yuan LIAO ,  Tzu-Jin YEH ,  Ying-Ta LU

    IPC: H01L23/522 ,  H01L49/02 ,  H01L23/58 ,  H01L23/528 ,  H01L23/00 ,  H01L23/64

    Abstract: An integrated circuit includes an inductor that includes a first set of conductive lines in a first metal layer, and is over a substrate, and a guard ring. The guard ring includes a first conductive line in a second metal layer, and extending in a first direction, a second conductive line extending in a second direction, and a first staggered line coupled between the first conductive line and the second conductive line. The first staggered line includes a second set of conductive lines in the second metal layer, and extends in the first direction, a third set of conductive lines in a third metal layer, and extends in the second direction, and a first set of vias coupling the second and third set of conductive lines together. All metal lines in the third metal layer that are part of the guard ring extend in the second direction.

    METHOD OF FORMING A SEMICONDUCTOR DEVICE
    19.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200168730A1

    公开(公告)日：2020-05-28

    申请号：US16774855

    申请日：2020-01-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chewn-Pu JOU ,  Tzu-Jin YEH ,  Chia-Chung CHEN

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A method of making a semiconductor device includes depositing an isolation region between adjacent fins of a plurality of fins over a substrate, wherein a top-most surface of the isolation region is a first distance from a bottom of the substrate. The method further includes doping each of the plurality of fins with a first dopant having a first dopant type to define a first doped region in each of the plurality of fins, wherein a bottom-most surface of the first doped region is a second distance from the bottom of the substrate, and the second distance is greater than the first distance. The method further includes doping each of the plurality of fins with a second dopant having a second dopant type to define a second doped region in each of the plurality of fins, wherein the second doped region contacts the isolation region.

    PHASE SHIFTER CIRCUIT, PHASE SHIFTER LAYOUT AND METHOD OF FORMING THE SAME
    20.
    发明申请
    PHASE SHIFTER CIRCUIT, PHASE SHIFTER LAYOUT AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20200004920A1

    公开(公告)日：2020-01-02

    申请号：US16442178

    申请日：2019-06-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chi-Hsien LIN ,  Ho-Hsiang CHEN ,  Hsien-Yuan LIAO ,  Tzu-Jin YEH ,  Ying-Ta LU

    IPC: G06F17/50 ,  G03F1/36 ,  G03F1/70

    Abstract: A phase shifter includes an active region, a first and a second set of gates and a set of contacts. The active region extends in a first direction and is located at a first level. The first and second set of gates each extend in a second direction, overlap the active region and are located at a second level. The second set of gates are positioned along opposite edges of the active region, are configured to receive a first voltage, and are part of a first transistor. The first transistor is configured to adjust a first capacitance of the phase shifter responsive to the first voltage. The set of contacts extend in the second direction, are over the active region, are located at a third level, and are positioned between at least the second set of gates.

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