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公开(公告)号：US09141754B2
公开(公告)日：2015-09-22
申请号：US14489155
申请日：2014-09-17
CPC分类号： G06F17/5081 , G06F17/5009 , G06F2217/02 , G06F2217/06 , G06F2217/08 , G06F2217/12 , H01L27/0207 , H01L29/94
摘要： A method comprises generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also comprises generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further comprises selecting a layout generation configuration for generating the layout of semiconductor components. The method additionally comprises generating the layout of semiconductor components based on the selected layout generation configuration.
摘要翻译： 一种方法包括生成半导体部件布局的第一组配置。 第一组配置的配置各自满足一组设计规则的第一子集。 该方法还包括生成半导体部件布局的第二组配置。 第二组配置是通过消除第一组配置的一个或多个配置而基于确定所述第一组配置的消除的一个或多个配置不能满足该组设计规则的第二子集来生成的 。 该方法还包括选择用于生成半导体部件的布局的布局生成配置。 该方法还包括基于所选择的布局生成配置来生成半导体部件的布局。
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公开(公告)号：US12094872B2
公开(公告)日：2024-09-17
申请号：US17643651
申请日：2021-12-10
发明人： Chung-Hui Chen , Wan-Te Chen , Shu-Wei Chung , Tung-Heng Hsieh , Tzu-Ching Chang , Tsung-Hsin Yu , Yung Feng Chang
IPC分类号： H01L27/06 , H01L29/06 , H01L29/423 , H01L29/786
CPC分类号： H01L27/0629 , H01L29/0653 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.
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公开(公告)号：US12068306B2
公开(公告)日：2024-08-20
申请号：US18312219
申请日：2023-05-04
IPC分类号： H01L27/02 , G06F30/3953 , H01L23/522 , H01L23/528
CPC分类号： H01L27/0207 , G06F30/3953 , H01L23/5226 , H01L23/528
摘要： An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first transistor and a second transistor over the first side of the substrate, a first conductive pattern over the first side of the substrate, and a second conductive pattern under the second side of the substrate. The first conductive pattern electrically couples a first terminal of the first transistor to a second terminal of the second transistor. The second conductive pattern electrically couples the first terminal of the first transistor to the second terminal of the second transistor.
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公开(公告)号：US11676957B2
公开(公告)日：2023-06-13
申请号：US17189908
申请日：2021-03-02
IPC分类号： H01L27/02 , G06F30/3953 , H01L23/528 , H01L23/522
CPC分类号： H01L27/0207 , G06F30/3953 , H01L23/528 , H01L23/5226
摘要： An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first conductive pattern over the active region, and a second conductive pattern under the second side of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically coupled to the first portion and the second portion of the active region. The second conductive pattern is electrically coupled to the first portion and the second portion of the active region.
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公开(公告)号：US11562953B2
公开(公告)日：2023-01-24
申请号：US16660363
申请日：2019-10-22
发明人： Chung-Hui Chen , Hao-Chieh Chan
IPC分类号： H01L23/528 , H01L23/50 , H01L23/522 , G06F30/39 , H01L21/8238
摘要： An integrated circuit includes two parallel active zones extending in a first direction, an n-type pick-up region, and a p-type pick-up region. The two parallel active zones includes a p-type active zone located in an n-type well and an n-type active zone located in a p-type well. The n-type pick-up region is located in the n-type well and configured to have a first supply voltage. The p-type pick-up region is located in the p-type well and configured to have a second supply voltage, wherein the second supply voltage is lower than the first supply voltage. The n-type pick-up region and the p-type pick-up region are separated from each other along a direction that is different from the first direction.
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公开(公告)号：US11494542B2
公开(公告)日：2022-11-08
申请号：US16741440
申请日：2020-01-13
发明人： Chung-Hui Chen , Tzu Ching Chang , Wan-Te Chen
IPC分类号： G06F30/392 , H01L23/522 , G03F1/70 , G06F30/3953 , G06F30/398
摘要： A semiconductor device includes: an active area in a transistor layer; contact-source/drain (CSD) conductors in the transistor layer; gate conductors in the transistor layer, and interleaved with the CSD conductors; VG structures in the transistor layer, and over the active area; and a first gate-signal-carrying (GSC) conductor in an M_1st layer that is over the transistor layer, and that is over the active area; and wherein long axes correspondingly of the active area and the first GSC conductor extend substantially in a first direction; and long axes correspondingly of the CSD conductors and the gate conductors extend substantially in a second direction, the second direction being substantially perpendicular to the first direction.
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公开(公告)号：US10720361B2
公开(公告)日：2020-07-21
申请号：US16512041
申请日：2019-07-15
发明人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
IPC分类号： H01L27/07 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L49/02 , H01L29/94 , H01L29/40
摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.
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公开(公告)号：US10510826B2
公开(公告)日：2019-12-17
申请号：US15966406
申请日：2018-04-30
发明人： Hao-Chieh Chan , Chung-Hui Chen
IPC分类号： H01L49/02 , H01L23/522 , H01L21/8234 , H01L27/088 , H01L21/762 , H01L29/78 , H01L29/66 , H01L27/08 , H01L27/06 , H01L29/94 , H01L27/02
摘要： A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.
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公开(公告)号：US09354124B2
公开(公告)日：2016-05-31
申请号：US14193563
申请日：2014-02-28
发明人： Jaw-Juinn Horng , Szu-Lin Liu , Chung-Hui Chen
CPC分类号： G01K7/01 , G01R19/0084
摘要： A circuit includes a comparator unit, a capacitive device, and a switching network. The comparator unit is configured to set a control signal at a first logical value when an output voltage reaches a first voltage value from being less than the first voltage value, and to set the control signal at a second logical value when the output voltage reaches a second voltage value from being greater than the second voltage. The capacitive device provides the output voltage. The switching network is configured to charge or discharge the capacitive device based on the control signal.
摘要翻译： 电路包括比较器单元，电容器件和开关网络。 比较器单元被配置为当输出电压达到小于第一电压值的第一电压值时，将控制信号设置在第一逻辑值，并且当输出电压达到第一逻辑值时将控制信号设置在第二逻辑值 第二电压值大于第二电压。 电容器件提供输出电压。 交换网络被配置为基于控制信号对电容性设备进行充电或放电。
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20.发明授权Guard structure for semiconductor structure and method of forming guard layout pattern for semiconductor layout pattern 有权半导体结构的保护结构和形成半导体布局图案的保护布局图案的方法公开(公告)号：US09093494B2
公开(公告)日：2015-07-28
申请号：US13781615
申请日：2013-02-28
发明人： Jaw-Juinn Horng , Jen-Hao Yeh , Fu-Chih Yang , Chung-Hui Chen
CPC分类号： H01L21/76 , H01L21/761 , H01L29/02 , H01L29/0619 , H01L29/0623 , H01L29/1083 , H01L29/7816
摘要： A guard structure for a semiconductor structure is provided. The guard structure includes a first guard ring, a second guard ring and a third guard ring. The first guard ring has a first conductivity type. The second guard ring has a second conductivity type, and surrounds the first guard ring. The third guard ring has the first conductivity type, and surrounds the second guard ring, wherein the first, the second and the third guard rings are grounded. A method of forming a guard layout pattern for a semiconductor layout pattern is also provided.
摘要翻译： 提供了半导体结构的保护结构。 防护结构包括第一保护环，第二保护环和第三保护环。 第一保护环具有第一导电类型。 第二保护环具有第二导电类型，并且围绕第一保护环。 第三保护环具有第一导电类型并围绕第二保护环，其中第一，第二和第三保护环接地。 还提供了形成半导体布局图案的保护布局图案的方法。
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