公开(公告)号：US11569164B2

公开(公告)日：2023-01-31

申请号：US16880336

申请日：2020-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Wen-Sheng Chen ,  An-Hsun Lo ,  En-Hsiang Yeh ,  Tzu-Jin Yeh

IPC: H01L23/522 ,  H01L49/02

Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.

公开(公告)号：US11555848B2

公开(公告)日：2023-01-17

申请号：US17376338

申请日：2021-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsieh-Hung Hsieh ,  Yen-Jen Chen ,  Tzu-Jin Yeh

IPC: G01R31/28

Abstract: A test circuit includes an oscillator configured to generate an oscillation signal, a device-under-test (DUT) configured to output an AC signal based on the oscillation signal, a first detection circuit configured to generate a first DC voltage having a first value based on the oscillation signal, and a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.

公开(公告)号：US11456711B2

公开(公告)日：2022-09-27

申请号：US17006892

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： En-Hsiang Yeh ,  Wen-Sheng Chen ,  Chia-Ming Liang ,  Chung-Ho Chai ,  Zong-You Li ,  Tzu-Jin Yeh

IPC: H03F1/22 ,  H03F3/195 ,  H03F3/24

Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.

公开(公告)号：US11177384B2

公开(公告)日：2021-11-16

申请号：US16774855

申请日：2020-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Chia-Chung Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A method of making a semiconductor device includes depositing an isolation region between adjacent fins of a plurality of fins over a substrate, wherein a top-most surface of the isolation region is a first distance from a bottom of the substrate. The method further includes doping each of the plurality of fins with a first dopant having a first dopant type to define a first doped region in each of the plurality of fins, wherein a bottom-most surface of the first doped region is a second distance from the bottom of the substrate, and the second distance is greater than the first distance. The method further includes doping each of the plurality of fins with a second dopant having a second dopant type to define a second doped region in each of the plurality of fins, wherein the second doped region contacts the isolation region.

公开(公告)号：US10931230B2

公开(公告)日：2021-02-23

申请号：US16432004

申请日：2019-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Hsien Lin ,  Ho-Hsiang Chen ,  Hsien-Yuan Liao ,  Tzu-Jin Yeh ,  Ying-Ta Lu

IPC: H03B1/04 ,  H03L7/099 ,  H01L23/528 ,  H01L23/522 ,  H01L23/66 ,  H03H7/01 ,  H03B5/12

Abstract: A voltage-controlled oscillator (VCO) includes a power supply node configured to have a power supply voltage. A reference node is configured to have a reference voltage. A transformer-coupled band-pass filter (BPF) is coupled to a pair of transistors. The pair of transistors and the transformer-coupled band-pass filter are positioned between the power supply node and the reference node.

公开(公告)号：US20190259715A1

公开(公告)日：2019-08-22

申请号：US16400419

申请日：2019-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chung Chen ,  Chi-Feng Huang ,  Shu Fang Fu ,  Tzu-Jin Yeh ,  Chewn-Pu Jou

IPC: H01L23/66 ,  H01L29/78 ,  H01L29/66 ,  H01L27/06 ,  H01L29/45 ,  H01L29/06 ,  H01L21/265 ,  H01L29/10 ,  H01L21/761 ,  H01L49/02 ,  H01L29/417 ,  H01L21/762

Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.

公开(公告)号：US10163779B2

公开(公告)日：2018-12-25

申请号：US14303206

申请日：2014-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chiao-Han Lee ,  Hsien-Yuan Liao ,  Ying-Ta Lu ,  Chi-Hsien Lin ,  Ho-Hsiang Chen ,  Tzu-Jin Yeh

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/58 ,  H01L23/64 ,  H01L23/522 ,  H01L49/02

Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.

公开(公告)号：US09633956B2

公开(公告)日：2017-04-25

申请号：US14860102

申请日：2015-09-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chung Chen ,  Chi-Feng Huang ,  Shu Fang Fu ,  Tzu-Jin Yeh ,  Chewn-Pu Jou

IPC: H01L21/00 ,  H01L29/78 ,  H01L21/336 ,  H01L27/085 ,  H01L21/70 ,  H01L23/66 ,  H01L29/417 ,  H01L29/66 ,  H01L21/761 ,  H01L29/10 ,  H01L21/762 ,  H01L21/265

CPC classification number: H01L23/66 ,  H01L21/26513 ,  H01L21/761 ,  H01L21/7624 ,  H01L27/0629 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.

公开(公告)号：US09374086B2

公开(公告)日：2016-06-21

申请号：US13673516

申请日：2012-11-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

IPC: H04B1/48 ,  H03K17/693

CPC classification number: H03K17/693 ,  H04B1/48

Abstract: A method of electrically coupling a first node and a second node of a switch cell includes biasing the second node and a bias node of the switch cell at a direct current (DC) voltage level of a second voltage level greater than a first voltage level. A first switch unit coupled between the first node and the second node is tuned on by a first control signal having a third voltage level. The third voltage level being greater than the first voltage level, and a difference between the third voltage level and the first voltage level is about twice a difference between the second voltage level and the first voltage level. Also, a second switch unit coupled between the second node and the bias node is turned off by a second control signal having the first voltage level.

Abstract translation: 电耦合开关单元的第一节点和第二节点的方法包括将第二节点和开关单元的偏置节点偏置在大于第一电压电平的第二电压电平的直流（DC）电压电平上。 耦合在第一节点和第二节点之间的第一开关单元由具有第三电压电平的第一控制信号调谐。 所述第三电压电平大于所述第一电压电平，并且所述第三电压电平与所述第一电压电平之间的差是所述第二电压电平与所述第一电压电平之差的大约两倍。 此外，耦合在第二节点和偏置节点之间的第二开关单元被具有第一电压电平的第二控制信号截止。

公开(公告)号：US08759181B2

公开(公告)日：2014-06-24

申请号：US13927340

申请日：2013-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/42372 ,  H01L29/785

Abstract: Methods for forming reduced gate resistance finFETs. Methods for a metal gate transistor structure are disclosed including forming a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Additional methods are disclosed.

Abstract translation: 用于形成栅极电阻finFET的方法。 公开了一种金属栅极晶体管结构的方法，包括形成在半导体衬底上形成的多个半导体鳍片，所述鳍片平行布置并间隔开; 一个含金属的栅电极，形成在半导体衬底之上，并且覆盖每个半导体鳍片的沟道栅极区域，并且在半导体鳍片之间的半导体衬底上延伸; 覆盖所述栅电极和所述半导体衬底的层间电介质层; 以及多个触点，其布置在所述层间电介质层中并且延伸穿过所述层间电介质层到所述栅电极; 形成在所述层间电介质层上并且由所述多个触点耦合到所述栅电极的低电阻金属带; 其中所述多个触点与所述半导体鳍片的沟道栅极区域间隔开。 公开了另外的方法。