THROUGH WAFER ISOLATION ELEMENT BACKSIDE PROCESSING

    公开(公告)号:US20220359268A1

    公开(公告)日:2022-11-10

    申请号:US17683201

    申请日:2022-02-28

    Abstract: Disclosed herein is an integrated circuit (IC) comprising a semiconductor wafer, a dielectric layer, and an isolation element. The semiconductor wafer has a first wafer portion and a second wafer portion each extending from a frontside surface to a backside surface. The dielectric layer interfaces with the first wafer portion and with the second wafer portion each on the frontside surface. The isolation element has an isolation dielectric material, and the isolation element extends between a first side surface of the first wafer portion and a second side surface of the second wafer portion and from an extension plane of the frontside surface to an extension plane of the backside surface. Also disclosed herein is a system comprising the IC and a package substrate coupled to the IC.

    SHAPE MEMORY POLYMER FOR USE IN SEMICONDUCTOR DEVICE FABRICATION

    公开(公告)号:US20210313241A1

    公开(公告)日:2021-10-07

    申请号:US17220782

    申请日:2021-04-01

    Abstract: A method for forming a semiconductor structure includes curing a shape memory polymer in a first shape. The shape memory polymer is coupled to a conductive layer. The method further includes folding the shape memory polymer from the first shape into a second shape. The method also includes bonding a semiconductor wafer to the conductive layer while the shape memory polymer is in the second shape. The semiconductor wafer has first and second dies. The semiconductor wafer is then singulated to separate the first die from the second die. The method further includes expanding the shape memory polymer to its first shape and singulating the shape memory polymer to separate the first and second dies.

Patent Agency Ranking