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    DUAL MODE MEMORY ARRAY SECURITY APPARATUS, SYSTEMS AND METHODS
    11.
    发明申请
    DUAL MODE MEMORY ARRAY SECURITY APPARATUS, SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20190019545A1

    公开(公告)日：2019-01-17

    申请号：US16120107

    申请日：2018-08-31

    Applicant: Texas Instruments Incorporated

    Inventor： Chiraag Juvekar ,  Joyce Kwong ,  Clive Bittlestone ,  Srinath Ramswamy

    IPC: G11C11/22 ,  H04L9/32 ,  H01L27/11507

    CPC classification number: G11C11/2295 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2277 ,  H01L27/11507 ,  H04L9/3278

    Abstract: Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.

    Apparatus and method for physically unclonable function (PUF) for a memory array
    12.
    发明授权
    Apparatus and method for physically unclonable function (PUF) for a memory array 有权

    公开(公告)号：US10152613B2

    公开(公告)日：2018-12-11

    申请号：US15898935

    申请日：2018-02-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joyce Kwong ,  Clive Bittlestone ,  Manish Goel

    IPC: G06F21/73 ,  G11C11/419 ,  G11C29/50 ,  G09C1/00 ,  H04L9/32 ,  G11C29/44

    Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.

    DUAL MODE MEMORY CELL APPARATUS AND METHODS
    17.
    发明申请
    DUAL MODE MEMORY CELL APPARATUS AND METHODS 审中-公开
    双模存储单元设备和方法

    公开(公告)号：US20160365510A1

    公开(公告)日：2016-12-15

    申请号：US15189114

    申请日：2016-06-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chiraag Juvekar ,  Joyce Kwong ,  Clive Bittlestone ,  Srinath Ramaswamy ,  Stephen Heinrich-Barna

    IPC: H01L43/12 ,  H01L27/115 ,  H01L21/66 ,  G11C11/22

    CPC classification number: H01L43/12 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C2211/4013 ,  H01L22/14 ,  H01L27/115

    Abstract: Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.

    Abstract translation: 要永久打印在存储器阵列的存储单元中的只读（“RO”）数据被写入存储器阵列。 然后将一个或多个过应力条件（例如热，过电压，过电流和/或机械应力）施加到存储器阵列或存储器阵列内的各个存储单元。 过应力条件作用于存储单元的一个或多个状态确定元件以压印RO数据。 过应力条件永久地改变状态确定元件的状态确定属性的值，而不会使存储单元的正常操作失效。 状态确定属性的改变值根据RO数据位的状态来偏移单元。 该偏置在细胞读出信号中是可检测的。 预制的铁电随机存取存储器（“FRAM”）阵列被烘烤。 烘焙陷阱电偶极子在与预写数据的状态相对应的方向上取向，并形成了RO数据压印。

    DUAL-MODE ERROR-CORRECTION CODE/WRITE-ONCE MEMORY CODEC
    18.
    发明申请
    DUAL-MODE ERROR-CORRECTION CODE/WRITE-ONCE MEMORY CODEC 有权
    双模式错误修正代码/写入存储器编解码器

    公开(公告)号：US20160342471A1

    公开(公告)日：2016-11-24

    申请号：US14720442

    申请日：2015-05-22

    Applicant: Texas Instruments Incorporated

    Inventor： Sai Zhang ,  Yuming Zhu ,  Clive Bittlestone ,  Srinath Ramaswamy

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1048 ,  G11C29/52 ,  H03M13/159 ,  H03M13/19 ,  H03M13/353 ,  H03M13/616

    Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Only Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.

    Abstract translation: 一次写入存储器（WOM）代码的纠错码（ECC）管理系统包括例如用于在WOM（只写存储器）模式和ECC（纠错码）模式之一中进行选择的控制器。 编解码器被布置为在选择的模式下操作。 以ECC模式操作的编解码器被配置为响应于第一接收数据字的ECC奇偶校验位来识别至少一个位错误的位位置。 在WOM模式下操作的编解码器被布置成从WOM设备中的寻址位置接收WOM编码的字，以接收待编码和写入到寻址位置的第二接收数据字，并且生成WOM编码字 用于写入WOM设备中的寻址位置。 用于写入寻址位置的WOM编码字可选地被ECC编码。

    ERROR CORRECTION CODE MANAGEMENT OF WRITE-ONCE MEMORY CODES
    19.
    发明申请
    ERROR CORRECTION CODE MANAGEMENT OF WRITE-ONCE MEMORY CODES 有权
    一般存储器代码的错误修正代码管理

    公开(公告)号：US20160328289A1

    公开(公告)日：2016-11-10

    申请号：US14703714

    申请日：2015-05-04

    Applicant: Texas Instruments Incorporated

    Inventor： Sai Zhang ,  Yuming Zhu ,  Clive Bittlestone ,  Srinath Ramaswamy

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/08 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1072 ,  G06F11/1076 ,  G06F12/0246 ,  G11C29/52 ,  H03M13/13

    Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a host processor is arranged to send a data word that is to be stored in a WOM (Write-Only Memory) device. A host interface is arranged to receive the first data word for processing by a WOM controller and an ECC controller. The WOM controller is for generating a first WOM-encoded word in response to an original symbol of the first data word, while the ECC controller is for generating a first set of ECC bits in response to the original symbol of the first data word. A memory device interface is for writing the first WOM-encoded word and the first set of ECC bits to the WOM device in accordance with the memory address associated with the first data word.

    Abstract translation: 一次写入存储器（WOM）代码的纠错码（ECC）管理系统包括例如主机处理器被配置为发送要存储在WOM（只写存储器）设备中的数据字。 主机接口被布置为接收第一数据字以供WOM控制器和ECC控制器处理。 WOM控制器用于响应于第一数据字的原始符号来生成第一WOM编码字，而ECC控制器用于响应于第一数据字的原始符号来生成第一组ECC位。 存储器件接口用于根据与第一数据字相关联的存储器地址将第一WOM编码字和第一组ECC位写入WOM器件。

    Dual mode ferroelectric random access memory (FRAM) cell apparatus and methods with imprinted read-only (RO) data
    20.
    发明授权
    Dual mode ferroelectric random access memory (FRAM) cell apparatus and methods with imprinted read-only (RO) data 有权
    双模式铁电随机存取存储器（FRAM）单元设备和具有压印只读（RO）数据的方法

    公开(公告)号：US09401196B1

    公开(公告)日：2016-07-26

    申请号：US14737247

    申请日：2015-06-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chiraag Juvekar ,  Joyce Kwong ,  Clive Bittlestone ,  Srinath Ramaswamy ,  Stephen K. Heinrich-Barna

    IPC: G11C11/22

    CPC classification number: H01L43/12 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C2211/4013 ,  H01L22/14 ,  H01L27/115

    Abstract: Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.

    Abstract translation: 要永久打印在存储器阵列的存储单元中的只读（“RO”）数据被写入存储器阵列。 然后将一个或多个过应力条件（例如热，过电压，过电流和/或机械应力）施加到存储器阵列或存储器阵列内的各个存储单元。 过应力条件作用于存储单元的一个或多个状态确定元件以压印RO数据。 过应力条件永久地改变状态确定元件的状态确定属性的值，而不会使存储单元的正常操作失效。 状态确定属性的改变值根据RO数据位的状态来偏移单元。 该偏置在细胞读出信号中是可检测的。 预制的铁电随机存取存储器（“FRAM”）阵列被烘烤。 烘焙陷阱电偶极子在与预写数据的状态相对应的方向上取向，并形成了RO数据压印。

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