公开(公告)号：US20190205132A1

公开(公告)日：2019-07-04

申请号：US15940283

申请日：2018-03-29

Applicant: Texas Instruments Incorporated

Inventor： Duc BUI ,  Dheera BALASUBRAMANIAN ,  Naveen BHORIA ,  Sahithi KRISHNA

IPC: G06F9/30 ,  G06F17/30

Abstract: Disclosed embodiments relate to look up table operations implemented in a digital data processor. A look up table read instruction recalls data elements of a specified data size from table(s) and stores recalled data elements in successive slots in a destination register. Disclosed embodiments promote data elements to a larger size with selected sign or zero extension. A source operand register stores vector offsets from a table start address. A destination operand stores the results of the look up table read. The look up table instruction implies a base address register and a configuration register. The base address register stores a table base address. The configuration register sets various look up table read operation parameters.

公开(公告)号：US20220188121A1

公开(公告)日：2022-06-16

申请号：US17688260

申请日：2022-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Duc BUI ,  Joseph ZBICIAK ,  Reid E. TATGE

IPC: G06F9/38

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

公开(公告)号：US20220188113A1

公开(公告)日：2022-06-16

申请号：US17686584

申请日：2022-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Dheera Balasubramanian SAMUDRALA

IPC: G06F9/30 ,  G11C11/409 ,  G06F12/02 ,  G06F16/31 ,  G06F16/901 ,  G06F16/41 ,  G06F9/445 ,  G06F9/38

Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to the instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The at least one operational unit is configured to perform a table write in response to a look up table write instruction by writing at least one data element from a source data register to a specified location in a specified number of at least one table.

公开(公告)号：US20210326136A1

公开(公告)日：2021-10-21

申请号：US17360646

申请日：2021-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Joseph ZBICIAK ,  Duc BUI ,  Mel Alan PHIPPS ,  Todd T. HAHN

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00 ,  G06F9/345

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, beginning execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, annulling the first instruction based on the execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction, and executing the second instruction.

公开(公告)号：US20200380035A1

公开(公告)日：2020-12-03

申请号：US16570874

申请日：2019-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Dheera Balasubramanian SAMUDRALA ,  Rama VENKATASUBRAMANIAN

IPC: G06F16/901 ,  G06F9/445 ,  G06F16/41 ,  G06F16/31

Abstract: A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.

公开(公告)号：US20200379763A1

公开(公告)日：2020-12-03

申请号：US16570778

申请日：2019-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Dheera Balasubramanian SAMUDRALA ,  Duc BUI ,  Rama VENKATASUBRAMANIAN

IPC: G06F9/30 ,  G06F12/02 ,  G11C11/409

Abstract: A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.

公开(公告)号：US20200210198A1

公开(公告)日：2020-07-02

申请号：US16685747

申请日：2019-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Duc BUI ,  Joseph ZBICIAK ,  Reid E. TATGE

IPC: G06F9/38 ,  G06F9/48

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor, the method comprising detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

公开(公告)号：US20190220276A1

公开(公告)日：2019-07-18

申请号：US16297824

申请日：2019-03-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Kai CHIRCA ,  Timothy D. ANDERSON ,  Duc BUI ,  Abhijeet A. CHACHAD ,  Son Hung TRAN

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/32 ,  G06F11/10

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/60

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.

公开(公告)号：US20250117247A1

公开(公告)日：2025-04-10

申请号：US18987011

申请日：2024-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc BUI ,  Timothy D. ANDERSON

IPC: G06F9/30

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.

公开(公告)号：US20240020125A1

公开(公告)日：2024-01-18

申请号：US18477657

申请日：2023-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Duc BUI ,  Dheera Balasubramanian SAMUDRALA ,  Rama VENKATASUBRAMANIAN

IPC: G06F9/30 ,  G11C11/409 ,  G06F12/02 ,  G06F9/38 ,  G06F16/31 ,  G06F16/901 ,  G06F16/41 ,  G06F9/445

CPC classification number: G06F9/30145 ,  G06F9/30105 ,  G11C11/409 ,  G06F12/0246 ,  G06F12/0292 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30101 ,  G06F9/3818 ,  G06F9/30043 ,  G06F9/30032 ,  G06F16/322 ,  G06F16/9017 ,  G06F16/41 ,  G06F9/44505 ,  G06F3/0647

Abstract: A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.