公开(公告)号：US20250112182A1

公开(公告)日：2025-04-03

申请号：US18478226

申请日：2023-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Masamitsu Matsuura ,  Daiki Komatsu ,  Kengo Aoya ,  Ting-Ta Yen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes a semiconductor wafer having a first connection pad and a second connection pad spaced apart by a semiconductor region of the semiconductor wafer. Portions of the semiconductor wafer are covered by a protective overcoat. The semiconductor package also includes a cap wafer mounted to the semiconductor wafer and overpassing the semiconductor region of the semiconductor wafer. The cap wafer extends between the first connection pad and the second connection pad of the semiconductor wafer. The semiconductor package further includes an insulation material overlaying the cap wafer. The insulation material comprising vias to the first connection pad and the second connection pad, the vias being filled with a conductive material.

公开(公告)号：US12040260B2

公开(公告)日：2024-07-16

申请号：US17139987

申请日：2020-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Ayumu Kuroda ,  Kengo Aoya

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49555 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48245 ,  H01L2224/85205

Abstract: An electronic package includes an electronic component including terminals, a plurality of surface contacts, at least some of the surface contacts being electrically coupled to the terminals within the electronic package, a mold compound covering the electronic component and partially covering the surface contacts with a bottom surface exposed from the mold compound, and a plurality of wires extending from exposed surfaces of the surface contacts, each of the wires providing a solderable surface for mounting the electronic package at a standoff on an external board.

公开(公告)号：US20230198422A1

公开(公告)日：2023-06-22

申请号：US18169113

申请日：2023-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Vivek Kishorechand Arora ,  Makoto Shibuya ,  Kengo Aoya

IPC: H02M7/527 ,  H02M3/00 ,  H01L29/16 ,  H02M7/00 ,  H01L29/20 ,  H02M3/158

CPC classification number: H02M7/527 ,  H02M3/003 ,  H01L29/1608 ,  H02M7/003 ,  H01L29/2003 ,  H02M3/1582

Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.

公开(公告)号：US11410875B2

公开(公告)日：2022-08-09

申请号：US16225875

申请日：2018-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hau Thanh Nguyen ,  Woochan Kim ,  Yi Yan ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar ,  Masamitsu Matsuura ,  Kengo Aoya ,  Mutsumi Masumoto

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00

Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).

公开(公告)号：US11183441B2

公开(公告)日：2021-11-23

申请号：US16808018

申请日：2020-03-03

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

公开(公告)号：US20190385924A1

公开(公告)日：2019-12-19

申请号：US16008119

申请日：2018-06-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00

Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

公开(公告)号：US20160240392A1

公开(公告)日：2016-08-18

申请号：US15137114

申请日：2016-04-25

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mark Allen Gerber ,  Mutsumi Masumoto ,  Masamitsu Matsuura ,  Kengo Aoya ,  Takeshi Onogami

IPC: H01L21/56 ,  H01L21/48

CPC classification number: H01L21/561 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.

公开(公告)号：US12272626B2

公开(公告)日：2025-04-08

申请号：US17683074

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya ,  Anindya Poddar

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.

公开(公告)号：US20250038009A1

公开(公告)日：2025-01-30

申请号：US18361747

申请日：2023-07-28

Applicant: Texas Instruments Incorporated

Inventor： Kengo Aoya ,  Masamitsu Matsuura ,  Daiki Komatsu

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

Abstract: A semiconductor package has a relief recess in the mold compound, extending around the perimeter over the leads. The relief recess has a relief width greater than a thickness of the leads under the relief recess. Top surfaces of the leads may be exposed at the relief recess, or may be covered by the mold compound under the relief recess. In both cases, a height difference between the mold compound under the relief recess and the leads under the relief recess is less than the thickness of the leads under the relief recess. A majority of exposed side faces of the leads are characteristic of sawn surfaces, which includes leads being free of vertical striations or having burrs along bottom edges. The semiconductor package is singulated by sawing through the leads.

公开(公告)号：US11848244B2

公开(公告)日：2023-12-19

申请号：US17491394

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L23/528 ,  H01L24/08 ,  H01L24/96 ,  H01L2224/08245 ,  H01L2224/08501

Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.