中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

82 records (took 0.023 seconds)

    Transistor with deep Nwell implanted through the gate
    11.
    发明授权
    Transistor with deep Nwell implanted through the gate 有权
    具有深Nwell的晶体管通过栅极植入

    公开(公告)号：US08981490B2

    公开(公告)日：2015-03-17

    申请号：US13827439

    申请日：2013-03-14

    Applicant: Texas Instruments Incorporated

    Inventor： Mahalingam Nandakumar

    IPC: H01L29/76 ,  H01L29/94 ,  H01L21/8236 ,  H01L29/78 ,  H01L21/336 ,  H01L29/778 ,  H01L27/092 ,  H01L21/8238

    CPC classification number: H01L27/0928 ,  H01L21/823814 ,  H01L21/823892

    Abstract: A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.

    Abstract translation: 制造CMOS集成电路（IC）的方法包括：以第一掩蔽级别注入第一n型掺杂剂，该第一掩模级别使其上具有第一栅极堆叠的衬底表面的p区域露出，以形成用于形成n源极/ 用于IC上的多个n沟道MOS（NMOS）晶体管的至少一部分的漏极延伸区域。 以第二掩蔽电平注入p型掺杂剂，其在其上具有第二栅极堆叠的衬底表面中露出n区，以形成用于至少部分多个p沟道MOS（PMOS）晶体管的PLDD区域 IC。 第二n型掺杂剂是逆向注入的，包括通过第一栅极叠层形成用于部分NMOS晶体管的深n阱（DNwell）。 与NLDD区域相比，DNwell的深度比第一个栅极堆叠更浅。

    Carbon and nitrogen doping for selected PMOS transistors on an integrated circuit
    13.
    发明授权
    Carbon and nitrogen doping for selected PMOS transistors on an integrated circuit 有权
    集成电路上选定的PMOS晶体管的碳氮掺杂

    公开(公告)号：US08853042B2

    公开(公告)日：2014-10-07

    申请号：US14148840

    申请日：2014-01-07

    Applicant: Texas Instruments Incorporated

    Inventor： Mahalingam Nandakumar ,  Amitabh Jain

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L21/265 ,  H01L29/10

    CPC classification number: H01L21/823412 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28202 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate.The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.

    Abstract translation: 形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。 与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。 包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。 源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。 在源极和漏极之间进行源极/漏极退火。

    High resistance poly resistor
    14.
    发明授权
    High resistance poly resistor 有权

    公开(公告)号：US12107117B2

    公开(公告)日：2024-10-01

    申请号：US18094088

    申请日：2023-01-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mahalingam Nandakumar

    IPC: H01L21/8234 ,  H01L23/525 ,  H01L27/06 ,  H01L29/76 ,  H01L49/02

    CPC classification number: H01L28/20 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5258 ,  H01L27/0629

    Abstract: An integrated circuit includes a polysilicon resistor having a plurality of segments, including first, second and third segments, the second segment located between and running about parallel to the first and third segments. A first header connects the first and second segments, and a second header connects the second and third segments. A first metal silicide layer located over the first header extends over the first and second segments toward the second header. A second metal silicide layer located over the second header extends over the second and third segments toward the first header. A dielectric layer is located over and contacts the first, second and third segments between the first and second metal silicide layers.

    SEMICONDUCTOR DEVICE WITH LOW NOISE TRANSISTOR AND LOW TEMPERATURE COEFFICIENT RESISTOR
    17.
    发明公开
    SEMICONDUCTOR DEVICE WITH LOW NOISE TRANSISTOR AND LOW TEMPERATURE COEFFICIENT RESISTOR 审中-公开

    公开(公告)号：US20230290775A1

    公开(公告)日：2023-09-14

    申请号：US18317227

    申请日：2023-05-15

    Applicant: Texas Instruments Incorporated

    Inventor： Mahalingam Nandakumar ,  Yanbiao Pan

    IPC: H01L27/06 ,  H01L21/8234

    CPC classification number: H01L27/0629 ,  H01L21/823418 ,  H01L21/823437

    Abstract: A semiconductor device includes a resistor having a resistor body including polysilicon, with fluorine in the polysilicon. The resistor body has a laterally alternating distribution of silicon grain sizes. The semiconductor device further includes an MOS transistor having a gate including polysilicon with fluorine. The fluorine in the gate has a higher average concentration than the fluorine in the resistor body. The semiconductor device may be formed by forming a gate/resistor layer including polysilicon. A fluorine implant mask is formed over the gate/resistor layer, exposing the gate/resistor layer in an area for the gate and over implant segments in an area for the resistor body. The implant segments do not cover the entire area for the resistor body. Fluorine is implanted into the gate/resistor layer where exposed by the fluorine implant mask. The gate/resistor layer is patterned to form the gate and the resistor body.

    SEMICONDUCTOR DEVICE WITH LOW NOISE TRANSISTOR AND LOW TEMPERATURE COEFFICIENT RESISTOR
    18.
    发明申请
    SEMICONDUCTOR DEVICE WITH LOW NOISE TRANSISTOR AND LOW TEMPERATURE COEFFICIENT RESISTOR 有权

    公开(公告)号：US20220139907A1

    公开(公告)日：2022-05-05

    申请号：US17086421

    申请日：2020-11-01

    Applicant: Texas Instruments Incorporated

    Inventor： Mahalingam Nandakumar ,  Yanbiao Pan

    IPC: H01L27/06 ,  H01L21/8234

    Abstract: A semiconductor device includes a resistor having a resistor body including polysilicon, with fluorine in the polysilicon. The resistor body has a laterally alternating distribution of silicon grain sizes. The semiconductor device further includes an MOS transistor having a gate including polysilicon with fluorine. The fluorine in the gate has a higher average concentration than the fluorine in the resistor body. The semiconductor device may be formed by forming a gate/resistor layer including polysilicon. A fluorine implant mask is formed over the gate/resistor layer, exposing the gate/resistor layer in an area for the gate and over implant segments in an area for the resistor body. The implant segments do not cover the entire area for the resistor body. Fluorine is implanted into the gate/resistor layer where exposed by the fluorine implant mask. The gate/resistor layer is patterned to form the gate and the resistor body.

Patent Agency Ranking