中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

25 records (took 0.027 seconds)

    Leakage compensation for a detector
    13.
    发明授权
    Leakage compensation for a detector 有权

    公开(公告)号：US11092482B2

    公开(公告)日：2021-08-17

    申请号：US16277653

    申请日：2019-02-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Nagesh Surendranath ,  Rakul Viswanath

    IPC: G01J1/44 ,  H03F1/26 ,  H03F3/08

    Abstract: A circuit for use in a system that includes a detector, wherein the circuit comprises an input terminal to receive a detector signal from the detector external to the circuit, the detector signal to include an error charge corresponding to a leakage current. The circuit further comprises an amplifier coupled to the input terminal to receive input signals corresponding to the detector signal, including the error charge applied to an input of the amplifier. The circuit further comprises a feedback path coupled across the amplifier, wherein the feedback path comprises a first switch coupled across a leakage resistor and to a leakage capacitor for discharging a feedback compensation charge from the leakage capacitor and onto the input of the amplifier to substantially cancel the error charge.

    Configurable analog-to-digital converter and processing for photon counting
    14.
    发明授权
    Configurable analog-to-digital converter and processing for photon counting 有权

    公开(公告)号：US10151845B1

    公开(公告)日：2018-12-11

    申请号：US15667445

    申请日：2017-08-02

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Rakul Viswanath ,  Nagesh Surendranath ,  Goli Sravana Kumar

    IPC: G01T1/24

    Abstract: A photon counting system includes a photon sensor, a charge-sensitive amplifier (CSA) and an analog-to-digital converter (ADC). The CSA is configured to convert photon energy detected by the photon sensor to voltage pulses. The ADC is configured to digitize the voltage pulses generated by the CSA. The ADC includes successive approximation circuitry. The successive approximation circuitry includes an N-bit digital-to-analog converter (DAC), an N-bit successive approximation register (SAR), a plurality of N-bit registers, and a multiplexer configured to selectively route outputs of the SAR and outputs of the N-bit registers to the DAC for conversion to an analog signal.

    MULTI-SAMPLING IN X-RAY RECEIVER FOR NOISE REDUCTION
    15.
    发明申请
    MULTI-SAMPLING IN X-RAY RECEIVER FOR NOISE REDUCTION 审中-公开

    公开(公告)号：US20180180559A1

    公开(公告)日：2018-06-28

    申请号：US15900621

    申请日：2018-02-20

    Applicant: Texas Instruments Incorporated

    Inventor： Goli Sravana Kumar ,  Nagesh Surendranath

    IPC: G01N23/04 ,  H04N5/32 ,  H04N5/378 ,  A61B6/00 ,  H04N5/357

    CPC classification number: G01N23/04 ,  A61B6/42 ,  H04N5/32 ,  H04N5/3575 ,  H04N5/378

    Abstract: The disclosure provides a receiver with reduced noise. The receiver includes a photodiode that generates an input signal in response to received light pulses. A pixel switch is coupled to the photodiode. An operational amplifier is coupled to the photodiode through the pixel switch. A feedback capacitor and a reset switch are coupled between a first input port and an output port of the operational amplifier. A switched resistor network is coupled to the output port of the operational amplifier. A first switched capacitor network is coupled to the switched resistor network and samples a reset voltage. A second switched capacitor network is coupled to the switched resistor network and samples a signal voltage. A subtractor receives the reset voltage and the signal voltage, and generates a sample voltage. The second switched network comprises two or more capacitors.

    MULTI-SAMPLING IN X-RAY RECEIVER FOR NOISE REDUCTION
    16.
    发明申请
    MULTI-SAMPLING IN X-RAY RECEIVER FOR NOISE REDUCTION 审中-公开
    用于噪声减少的X射线接收机的多采样

    公开(公告)号：US20150268360A1

    公开(公告)日：2015-09-24

    申请号：US14658291

    申请日：2015-03-16

    Applicant: Texas Instruments Incorporated

    Inventor： Goli Sravana Kumar ,  Nagesh Surendranath

    IPC: G01T1/24 ,  G01N23/04

    CPC classification number: G01N23/04 ,  A61B6/42 ,  H04N5/32 ,  H04N5/3575 ,  H04N5/378

    Abstract: The disclosure provides a receiver with reduced noise. The receiver includes a photodiode that generates an input signal in response to received light pulses. A pixel switch is coupled to the photodiode. An operational amplifier is coupled to the photodiode through the pixel switch. A feedback capacitor and a reset switch are coupled between a first input port and an output port of the operational amplifier. A switched resistor network is coupled to the output port of the operational amplifier. A first switched capacitor network is coupled to the switched resistor network and samples a reset voltage. A second switched capacitor network is coupled to the switched resistor network and samples a signal voltage. A subtractor receives the reset voltage and the signal voltage, and generates a sample voltage. The second switched network comprises two or more capacitors.

    Abstract translation: 本公开提供了具有降低的噪声的接收机。 接收机包括响应于接收的光脉冲而产生输入信号的光电二极管。 像素开关耦合到光电二极管。 运算放大器通过像素开关耦合到光电二极管。 反馈电容器和复位开关耦合在运算放大器的第一输入端口和输出端口之间。 开关电阻网络耦合到运算放大器的输出端口。 第一开关电容器网络耦合到开关电阻网络并对复位电压进行采样。 第二开关电容器网络耦合到开关电阻网络并对信号电压进行采样。 减法器接收复位电压和信号电压，并产生采样电压。 第二交换网络包括两个或更多个电容器。

    Circuit for Integrating Currents from High-Density Sensors
    17.
    发明公开
    Circuit for Integrating Currents from High-Density Sensors 审中-公开

    公开(公告)号：US20240106404A1

    公开(公告)日：2024-03-28

    申请号：US17955503

    申请日：2022-09-28

    Applicant: Texas Instruments Incorporated

    Inventor： Nagesh Surendranath ,  Eduardo Bartolome ,  Saugata Datta

    IPC: H03G1/04 ,  H03F1/26 ,  H03F3/45 ,  H03G3/30

    CPC classification number: H03G1/04 ,  H03F1/26 ,  H03F3/45475 ,  H03G3/3031

    Abstract: A circuit includes a plurality of first stage integrators. Each of the plurality of first stage integrators includes a first input, a second input, a third input and an output. The first input of each of the plurality of first stage integrators is coupled to a different one of circuit inputs, the second input is coupled to a first reference input, the third input is coupled to a second reference input and the output of each of the plurality of first stage integrators is coupled to the first input of such first stage integrator. The circuit includes a second stage integrator which includes a first input coupled to each of the first inputs of the plurality of first stage integrators, a second input coupled to the first reference input, and an output coupled to the first input of the second stage integrator.

Patent Agency Ranking