公开(公告)号：US12050541B2

公开(公告)日：2024-07-30

申请号：US18186524

申请日：2023-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Kishon Vijay Abraham Israel Vijayponraj ,  Mihir Narendra Mody ,  Jason A. T. Jones

IPC: G06F13/16 ,  G06F12/10 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F12/10 ,  G06F13/4022 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

公开(公告)号：US11853199B2

公开(公告)日：2023-12-26

申请号：US17538662

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Kishon Vijay Abraham Israel Vijayponraj ,  Mihir Narendra Mody ,  Vijaya Rama Raju Kanumuri ,  Cory Dean Stewart

IPC: G06F12/00 ,  G06F12/02 ,  G06F9/46 ,  G06F12/06

CPC classification number: G06F12/0238 ,  G06F9/467 ,  G06F12/0292 ,  G06F12/063

Abstract: A system is provided. In some examples, the system includes a first peripheral circuit and a memory management circuit coupled to the first peripheral circuit. The memory management circuit comprises a first table that associates virtual identification values with address space select values. The system also includes a transaction mapper circuit coupled to the memory management circuit. The transaction mapper circuit comprises a second table that associates virtual identification values with bus-device-function values.

公开(公告)号：US20230333858A1

公开(公告)日：2023-10-19

申请号：US17721534

申请日：2022-04-15

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Shailesh Ghotgalkar ,  Kedar Chitnis

IPC: G06F9/4401 ,  H04L9/32

CPC classification number: G06F9/4401 ,  H04L9/3247

Abstract: An example apparatus includes: a first interface configured to couple to a processor core; a second interface configured to couple to a first memory configured to store an image that includes a set of slices; a third interface coupled to the first interface, the third interface configured to couple to a second memory; a direct memory access circuit coupled to the second interface and the third interface and configured to: receive a transaction from the second interface, wherein the transaction specifies a read of a slice of the set of slices; and based on the transaction: read the slice from the first memory; perform on-the-fly operations to the slice; and store the slice in the second memory.

公开(公告)号：US11436024B2

公开(公告)日：2022-09-06

申请号：US16700254

申请日：2019-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Denis Roland Beaudoin ,  Gregory Raymond Shurtz ,  Santhanakrishnan Badri Narayanan ,  Mark Adrian Bryans ,  Mihir Narendra Mody ,  Jason A. T. Jones ,  Jayant Thakur

IPC: G06F9/4401 ,  H04L45/00 ,  H04L47/32 ,  G06F13/28 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US20210263883A1

公开(公告)日：2021-08-26

申请号：US17314313

申请日：2021-05-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jason A.T. Jones ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Kishon Vijay Abraham Israel Vijayponraj ,  Bradley Douglas Cobb ,  Sanand Prasad ,  Gregory Raymond Shurtz ,  Martin Jeffrey Ambrose ,  Jayant Thakur

IPC: G06F15/78 ,  G06F13/10

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

公开(公告)号：US11030144B2

公开(公告)日：2021-06-08

申请号：US16221364

申请日：2018-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jason A. T. Jones ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Kishon Vijay Abraham Israel Vijayponraj ,  Bradley Douglas Cobb ,  Sanand Prasad ,  Gregory Raymond Shurtz ,  Martin Jeffrey Ambrose ,  Jayant Thakur

IPC: G06F15/78 ,  G06F13/10

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

公开(公告)号：US12242377B2

公开(公告)日：2025-03-04

申请号：US18496178

申请日：2023-10-27

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Kishon Vijay Abraham Israel Vijayponraj ,  Mihir Narendra Mody ,  Vijaya Rama Raju Kanumuri ,  Cory Dean Stewart

IPC: G06F12/00 ,  G06F9/46 ,  G06F12/02 ,  G06F12/06

Abstract: Transaction mappers, methods and systems are provided. An example transaction mapper includes a table that associates virtual identification values with bus-device-function (BDF) values; and a firewall that receives an input-output request including a first virtual identification value of the virtual identification values, the first virtual identification value being associated with a function of an external peripheral, generates a first BDF value and a first traffic class value based on the table and the first virtual identification value, determine whether the first virtual identification value satisfies a threshold range, and determine whether to forward the input-output request to an external host device based on whether the first virtual identification value satisfies the threshold range.

公开(公告)号：US11947832B2

公开(公告)日：2024-04-02

申请号：US17668052

申请日：2022-02-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Mihir Mody

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/28 ,  G06F2213/28

Abstract: An integrated circuit is presented. The integrated circuit has a set of sensor input interfaces and an output interface. The integrated circuit further has a memory with a first and second memory locations. The integrated circuit further has a multi-chip hub module which has a transaction buffer with both a real-time and a non-real-time buffer. The multi-chip hub module has a context mapper, a re-formatter module and an error handling module. The context mapper is configured to map data to the first or second memory location. The multi-chip hub module is configured to process data through the modules and provide processed data to the output interface.

公开(公告)号：US11714776B2

公开(公告)日：2023-08-01

申请号：US17564975

申请日：2021-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kishon Vijay Abraham Israel Vijayponraj ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody

IPC: G06F13/42 ,  G06F9/4401 ,  G06F13/40 ,  G06F12/1027

CPC classification number: G06F13/4247 ,  G06F12/1027 ,  G06F13/4022 ,  G06F2213/0024 ,  G06F2213/0026 ,  G06F2213/0038

Abstract: A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

公开(公告)号：US11704263B2

公开(公告)日：2023-07-18

申请号：US17697114

申请日：2022-03-17

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Kishon Vijay Abraham Israel Vijayponraj ,  Mihir Narendra Mody

IPC: G06F13/20 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.