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    Non-Volatile Array Wakeup and Backup Sequencing Control
    11.
    发明申请
    Non-Volatile Array Wakeup and Backup Sequencing Control 有权
    非易失性阵列唤醒和备份排序控制

    公开(公告)号：US20140075225A1

    公开(公告)日：2014-03-13

    申请号：US13770280

    申请日：2013-02-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F1/32

    CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    Abstract: Individual first ones of a plurality of non-volatile logic element arrays are designated to restore first in response to entering a wakeup or restoration mode. These non-volatile logic element arrays include instructions for an order in which other non-volatile logic element arrays are to be restored next. So configured, the processing device can be set to have one or more NVL arrays restored first, which arrays are pre-configured to guide further wakeup of the device through directed restoration from particular NVL arrays. Certain NVL arrays can be skipped if the functions stored therein are not needed, and the order of restoration of others can be tailored to a particular wakeup time and power concern through restoration in parallel, serial, or combinations thereof.

    Abstract translation: 多个非易失性逻辑元件阵列中的单独的第一个被指定为响应于进入唤醒或恢复模式而首先恢复。 这些非易失性逻辑元件阵列包括用于下一步要恢复其它非易失性逻辑元件阵列的顺序的指令。 如此配置，处理设备可被设置为首先恢复一个或多个NVL阵列，这些阵列被预配置为通过从特定NVL阵列的定向恢复来引导设备进一步唤醒。 如果不需要存储在其中的功能，则可以跳过某些NVL阵列，并且通过并行，串行或其组合的恢复，可以针对特定的唤醒时间和功率需求来调整其他的恢复顺序。

    Nonvolatile Logic Array With Retention Flip Flops To Reduce Switching Power During Wakeup
    12.
    发明申请
    Nonvolatile Logic Array With Retention Flip Flops To Reduce Switching Power During Wakeup 有权
    具有保持触发器的非易失性逻辑阵列，以在唤醒期间降低开关电源

    公开(公告)号：US20140075089A1

    公开(公告)日：2014-03-13

    申请号：US13770368

    申请日：2013-02-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F12/02

    CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A processing device is operated using a plurality of volatile storage elements. Data in the plurality of volatile storage elements is stored in a plurality of non-volatile logic element arrays. A primary logic circuit portion of individual ones of the plurality of volatile storage elements is powered by a first power domain, and a slave stage circuit portion of individual ones of the plurality of volatile storage elements is powered by a second power domain. During a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the first power domain is powered down and the second power domain is maintained. In a further approach, the plurality of non-volatile logic element arrays is powered by a third power domain, which is powered down during regular operation of the processing device.

    Abstract translation: 使用多个易失性存储元件来操作处理装置。 多个易失性存储元件中的数据被存储在多个非易失性逻辑元件阵列中。 多个易失性存储元件中的各个易失性存储元件的主要逻辑电路部分由第一电源域供电，并且多个易失性存储元件中的单个的易失性存储元件的从属级电路部分由第二电源域供电。 在从多个非易失性逻辑单元阵列向多个易失性存储元件的数据写回期间，第一功率域被断电并维持第二功率域。 在另一种方法中，多个非易失性逻辑单元阵列由第三功率域供电，该第三功率域在处理设备的常规操作期间被关断。

    Processing Device With Nonvolatile Logic Array Backup
    13.
    发明申请
    Processing Device With Nonvolatile Logic Array Backup 审中-公开
    具有非易失性逻辑阵列备份的处理器件

    公开(公告)号：US20140075088A1

    公开(公告)日：2014-03-13

    申请号：US13770304

    申请日：2013-02-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F3/06

    CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

    Abstract translation: 使用多个易失性存储元件来操作处理装置。 每个组的多个易失性存储元件的N组M个易失性存储元件使用多路复用器连接到多个非易失性逻辑元件阵列的N×M个非易失性逻辑元件阵列。 多路复用器将N个组中的一个连接到N个M大小的非易失性逻辑单元阵列，以将来自M个易失性存储元件的数据一次存储为N个M大小的非易失性逻辑单元阵列的行或写入 数据一次从N个M大小的非易失性逻辑元件阵列的一行移动到M个易失性存储元件。 相应的非易失性逻辑控制器控制关于易失性存储元件和非易失性存储元件之间的连接的复用器操作。

    Processing device with nonvolatile logic array backup
    16.
    发明授权
    Processing device with nonvolatile logic array backup 有权

    公开(公告)号：US10468079B2

    公开(公告)日：2019-11-05

    申请号：US16159433

    申请日：2018-10-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G11C7/22 ,  G06F3/06 ,  H03K3/3562 ,  G06F12/02 ,  G06F9/4401 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3287 ,  G06F13/00 ,  G06F11/14 ,  G06F11/10 ,  G11C14/00

    Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

    Compute through power loss hardware approach for processing device having nonvolatile logic memory
    17.
    发明授权
    Compute through power loss hardware approach for processing device having nonvolatile logic memory 有权

    公开(公告)号：US10331203B2

    公开(公告)日：2019-06-25

    申请号：US15016449

    申请日：2016-02-05

    Applicant: Texas Instruments Incorporated

    Inventor： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F1/3293 ,  G06F1/3287 ,  G06F3/06 ,  G06F11/07 ,  G06F1/3206

    Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

    PROCESSING DEVICE WITH NONVOLATILE LOGIC ARRAY BACKUP
    18.
    发明申请
    PROCESSING DEVICE WITH NONVOLATILE LOGIC ARRAY BACKUP 审中-公开

    公开(公告)号：US20190043544A1

    公开(公告)日：2019-02-07

    申请号：US16159433

    申请日：2018-10-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G11C7/22 ,  G06F3/06 ,  H03K3/3562 ,  G11C14/00 ,  G06F9/4401 ,  G06F1/32 ,  G06F11/10 ,  G06F12/02 ,  G06F11/14 ,  G06F13/00

    Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

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