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    POWER CONVERTER MODULE
    14.
    发明公开
    POWER CONVERTER MODULE 审中-公开

    公开(公告)号：US20230198422A1

    公开(公告)日：2023-06-22

    申请号：US18169113

    申请日：2023-02-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Woochan Kim ,  Vivek Kishorechand Arora ,  Makoto Shibuya ,  Kengo Aoya

    IPC: H02M7/527 ,  H02M3/00 ,  H01L29/16 ,  H02M7/00 ,  H01L29/20 ,  H02M3/158

    CPC classification number: H02M7/527 ,  H02M3/003 ,  H01L29/1608 ,  H02M7/003 ,  H01L29/2003 ,  H02M3/1582

    Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.

    Stress buffer layer in embedded package
    15.
    发明授权
    Stress buffer layer in embedded package 有权

    公开(公告)号：US11183441B2

    公开(公告)日：2021-11-23

    申请号：US16808018

    申请日：2020-03-03

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

    SEMICONDUCTOR PACKAGE WITH ISOLATED HEAT SPREADER
    16.
    发明申请
    SEMICONDUCTOR PACKAGE WITH ISOLATED HEAT SPREADER 有权

    公开(公告)号：US20210202357A1

    公开(公告)日：2021-07-01

    申请号：US16840407

    申请日：2020-04-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Anindya Poddar ,  Woochan Kim ,  Vivek Kishorechand Arora

    IPC: H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

    Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

    Stress Buffer Layer in Embedded Package
    17.
    发明申请
    Stress Buffer Layer in Embedded Package 审中-公开

    公开(公告)号：US20190385924A1

    公开(公告)日：2019-12-19

    申请号：US16008119

    申请日：2018-06-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00

    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

    Heat slug attached to a die pad for semiconductor package
    18.
    发明授权
    Heat slug attached to a die pad for semiconductor package 有权

    公开(公告)号：US12136588B2

    公开(公告)日：2024-11-05

    申请号：US17379934

    申请日：2021-07-19

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Vivek Kishorechand Arora

    IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/482

    Abstract: A semiconductor package includes a leadframe including leads and a die attach pad (DAP) inside the leads, and at least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side attached to a bottom side portion of the DAP. The package includes a mold compound and a heat slug having a top side and a bottom side positioned within a cavity defined by sidewalls of the mold compound. The heat slug has an area greater than an area of the DAP is attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. Bondwires are between the leads and the bond pads. Exposed from the mold compound is a bottom side surfaces of the leads and the top side of the heat slug.

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