公开(公告)号：US20190259777A1

公开(公告)日：2019-08-22

申请号：US16398386

申请日：2019-04-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhito YOSHIMIZU ,  Akifumi GAWASE ,  Kei WATANABE ,  Shinya ARAI

IPC: H01L27/11582 ,  H01L21/764

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.

公开(公告)号：US20180083033A1

公开(公告)日：2018-03-22

申请号：US15824396

申请日：2017-11-28

Applicant: Toshiba Memory Corporation

Inventor： Shinya ARAI

IPC: H01L27/11582

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

公开(公告)号：US20210288073A1

公开(公告)日：2021-09-16

申请号：US17335214

申请日：2021-06-01

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20210210508A1

公开(公告)日：2021-07-08

申请号：US17206763

申请日：2021-03-19

Applicant: Toshiba Memory Corporation

Inventor： Shinya ARAI

IPC: H01L27/11582 ,  G11C16/04 ,  H01L21/28 ,  H01L49/02 ,  G11C16/26 ,  H01L27/11568

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

公开(公告)号：US20210202523A1

公开(公告)日：2021-07-01

申请号：US17200987

申请日：2021-03-15

Applicant: Toshiba Memory Corporation

Inventor： Shinya ARAI

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L21/764 ,  H01L29/06 ,  G11C16/14 ,  H01L27/11573 ,  H01L27/11556

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

公开(公告)号：US20210126003A1

公开(公告)日：2021-04-29

申请号：US17143632

申请日：2021-01-07

Applicant: Toshiba Memory Corporation

Inventor： Kotaro FUJII ,  Jun FUJIKI ,  Shinya ARAI

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.

公开(公告)号：US20200043944A1

公开(公告)日：2020-02-06

申请号：US16596892

申请日：2019-10-09

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20190333928A1

公开(公告)日：2019-10-31

申请号：US16298865

申请日：2019-03-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi NAGASHIMA ,  Keisuke NAKATSUKA ,  Fumitaka ARAI ,  Shinya ARAI ,  Yasuhiro UCHIYAMA

IPC: H01L27/11578 ,  H01L27/1157 ,  G11C11/40

Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.

公开(公告)号：US20190296046A1

公开(公告)日：2019-09-26

申请号：US16438769

申请日：2019-06-12

Applicant: Toshiba Memory Corporation

Inventor： Shinya ARAI

IPC: H01L27/11582 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L21/764 ,  H01L29/06 ,  H01L27/11573

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

公开(公告)号：US20190198524A1

公开(公告)日：2019-06-27

申请号：US16129082

申请日：2018-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun FUJIKI ,  Shinya ARAI ,  Kotaro FUJII

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/07 ,  H01L21/768

Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.