公开(公告)号：US20190296042A1

公开(公告)日：2019-09-26

申请号：US16127500

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroshi NAKAKI ,  Kotaro FUJII

IPC: H01L27/11582 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor memory device includes forming a plurality of connection portions on a plurality of main body portions by filling a semiconductor material into a plurality of second through-holes, and after the forming of the plurality of connection portions, removing the third layer and a remaining portion of the second layer, the remaining portion of the second layer not being removed in the removing of the portion of the second layer.

公开(公告)号：US20190296040A1

公开(公告)日：2019-09-26

申请号：US16122258

申请日：2018-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kotaro FUJII ,  Masahisa SONODA ,  Masaru KITO ,  Satoshi NAGASHIMA ,  Shigeki KOBAYASHI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/14 ,  G11C16/08

Abstract: A semiconductor device according to an embodiment includes first conductors, first pillars, a pillar column. Each of the first pillars is provided through the first conductors. The pillar column includes second pillars that are aligned in a first direction. Each of the second pillars is provided through the first conductors. The pillar column includes first and second columns of the second pillars. The first and second columns of the second pillars are aligned in a second direction that intersects the first direction. The first pillars are arranged on both sides in the second direction of each pillar column. The first conductors are provided continuously on both sides in the second direction of the second pillars that are included in each pillar column.

公开(公告)号：US20210126003A1

公开(公告)日：2021-04-29

申请号：US17143632

申请日：2021-01-07

Applicant: Toshiba Memory Corporation

Inventor： Kotaro FUJII ,  Jun FUJIKI ,  Shinya ARAI

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.

公开(公告)号：US20200075622A1

公开(公告)日：2020-03-05

申请号：US16284128

申请日：2019-02-25

Applicant: Toshiba Memory Corporation

Inventor： Kotaro FUJII ,  Satoshi NAGASHIMA ,  Yumi NAKAJIMA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/8234 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor memory device includes: a first insulating layer provided between first and second interconnection layers; a first semiconductor layer provided between the first interconnection layer and the first insulating layer; a second semiconductor layer provided between the second interconnection layer and the first insulating layer; a first charge storage layer provided between the first interconnection layer and the first semiconductor layer; a second charge storage layer provided between the second interconnection layer and the second semiconductor layer; and a second insulating layer provided between the first interconnection layer and the second interconnection layer, between the first semiconductor layer and the second semiconductor layer, and between the first charge storage layer and the second charge storage layer.

公开(公告)号：US20190198524A1

公开(公告)日：2019-06-27

申请号：US16129082

申请日：2018-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun FUJIKI ,  Shinya ARAI ,  Kotaro FUJII

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/07 ,  H01L21/768

Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.

公开(公告)号：US20180247951A1

公开(公告)日：2018-08-30

申请号：US15691931

申请日：2017-08-31

Applicant: Toshiba Memory Corporation

Inventor： Kotaro FUJII ,  Jun FUJIKI ,  Shinya ARAI

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.

公开(公告)号：US20200273876A1

公开(公告)日：2020-08-27

申请号：US16530741

申请日：2019-08-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takayuki KASHIMA ,  Kohei NYUI ,  Kotaro FUJII ,  Hiroyuki YAMASAKI

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor storage device includes a stacked body, a first semiconductor layer extending in the stacked body, a first charge storage layer disposed between the plurality of first conductor layers and the first semiconductor layer, a second conductor layer disposed above the stacked body, a second semiconductor layer extending through the second conductor layer, a third conductor layer disposed between the second semiconductor layer and the second conductor layer, a first insulator layer disposed above the third conductor layer, and a second insulator layer including a first portion disposed between the second semiconductor layer and the third conductor layer and a second portion disposed between the second semiconductor layer and the first insulator layer. A diameter of the second insulator layer is larger in the second portion than in the first portion.

公开(公告)号：US20190221576A1

公开(公告)日：2019-07-18

申请号：US16128103

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kotaro FUJII ,  Yasuhiro Uchiyama ,  Masaru Kito

IPC: H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device includes a first electrode film, a second electrode film separated from the first electrode film in a first direction, a third electrode film separated from the second electrode film in the first direction, a fourth electrode film separated from the third electrode film in the first direction, and a first and a second semiconductor members extending in the first direction. The second electrode film includes a first conductive portion, an insulating portion, and a second conductive portion arranged along a second direction. The first semiconductor member pierces the first, third and fourth electrode films and the insulating portion of the second electrode film. The second semiconductor member pierces the first, third and fourth electrode films, and the first conductive portion or the second conductive portion of the second electrode film.