公开(公告)号：US20200303408A1

公开(公告)日：2020-09-24

申请号：US16570067

申请日：2019-09-13

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Yuji SETTA ,  Masaru KITO

IPC: H01L27/11582 ,  H01L25/18 ,  H01L23/00 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11573 ,  H01L25/00

Abstract: In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.

公开(公告)号：US20200075461A1

公开(公告)日：2020-03-05

申请号：US16678007

申请日：2019-11-08

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Yoshiro SHIMOJO ,  Shinya ARAI

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11565

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

公开(公告)号：US20190088345A1

公开(公告)日：2019-03-21

申请号：US15918344

申请日：2018-03-12

Applicant: Toshiba Memory Corporation

Inventor： Michael Arnaud QUINSAT ,  Takuya SHIMADA ,  Susumu HASHIMOTO ,  Nobuyuki UMETSU ,  Yasuaki OOTERA ,  Masaki KADO ,  Tsuyoshi KONDO ,  Shiho NAKAMURA ,  Tomoya SANUKI ,  Yoshihiro UEDA ,  Yuichi ITO ,  Shinji MIYANO ,  Hideaki AOCHI ,  Yasuhito YOSHIMIZU

IPC: G11C19/08 ,  H01L43/08 ,  H01L43/10

CPC classification number: G11C19/0841 ,  G11C19/28 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.

公开(公告)号：US20220013367A1

公开(公告)日：2022-01-13

申请号：US17483052

申请日：2021-09-23

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Hiroyuki YASUI ,  Yuya AKEBOSHI ,  Fuyuma ITO

IPC: H01L21/306 ,  H01J37/32 ,  H01L21/67 ,  H01L21/02 ,  H01L21/311

Abstract: A plasma treatment apparatus includes a discharge device generating plasma under atmospheric pressure, and a nonmetallic tube capable of advancing the plasma generated in the discharge device. The discharge device includes a discharge body with an internal space, and the plasma being generated in the internal space. The nonmetallic tube is connected to the discharge body, and includes a material different from a material of the discharge body. The plasma is released from the nonmetallic tube to an environment under atmospheric pressure.

公开(公告)号：US20200075315A1

公开(公告)日：2020-03-05

申请号：US16296816

申请日：2019-03-08

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Fuyuma ITO ,  Naomi YANAI

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/033 ,  H01L21/324

Abstract: According to one embodiment, a substrate treating method includes: providing a first liquid onto a pattern on a substrate; providing, after the first liquid is provided, a second liquid containing a first substance to form a film containing the first substance on the pattern; providing, after the second liquid is provided onto the pattern, a third liquid; turning the third liquid into gas; and turning, after the third liquid is turned into gas, the film into gas.

公开(公告)号：US20190287598A1

公开(公告)日：2019-09-19

申请号：US16128554

申请日：2018-09-12

Applicant: Toshiba Memory Corporation

Inventor： Takuya SHIMADA ,  Yasuaki OOTERA ,  Tsuyoshi KONDO ,  Nobuyuki UMETSU ,  Michael Arnaud QUINSAT ,  Masaki KADO ,  Susumu HASHIMOTO ,  Shiho NAKAMURA ,  Hideaki AOCHI ,  Tomoya SANUKI ,  Shinji MIYANO ,  Yoshihiro UEDA ,  Yuichi ITO ,  Yasuhito YOSHIMIZU

IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01F10/32

Abstract: According to one embodiment, a magnetic memory device includes a first memory portion, a first conductive portion, a first interconnection, and a controller. The first memory portion includes a first magnetic portion including a first portion and a second portion, a first magnetic layer, and a first nonmagnetic layer provided between the second portion and the first magnetic layer. The first conductive portion is electrically connected to the first portion. The first interconnection is electrically connected to the first magnetic layer. The controller is electrically connected to the first conductive portion and the first interconnection. The controller applies a first pulse having a first pulse height and a first pulse length between the first conductive portion and the first interconnection in a first write operation and applies a second pulse having a second pulse height and a second pulse length in a first shift operation.

公开(公告)号：US20190237479A1

公开(公告)日：2019-08-01

申请号：US16381625

申请日：2019-04-11

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU

IPC: H01L27/11582 ,  H01L23/528 ,  H01L21/28 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/02 ,  H01L21/311

Abstract: A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.

公开(公告)号：US20190088305A1

公开(公告)日：2019-03-21

申请号：US15918304

申请日：2018-03-12

Applicant: Toshiba Memory Corporation

Inventor： Nobuyuki UMETSU ,  Tsuyoshi KONDO ,  Yasuaki OOTERA ,  Takuya SHIMADA ,  Michael Arnaud QUINSAT ,  Masaki KADO ,  Susumu HASHIMOTO ,  Shiho NAKAMURA ,  Tomoya SANUKI ,  Yoshihiro UEDA ,  Yuichi ITO ,  Shinji MIYANO ,  Hideeaki AOCHI ,  Yasuhito YOSHIMIZU

IPC: G11C11/16 ,  H01L27/22 ,  H01L23/528

Abstract: According to one embodiment, a magnetic memory device includes a magnetic portion, a first magnetic layer, a first nonmagnetic layer, a first element portion, first to third interconnects, and a controller. In a first operation, the controller sets the first interconnect to a first potential, the second interconnect to a second potential, and the third interconnect to a third potential. An absolute value of a difference between the second potential and the third potential is greater than that between the first potential and the third potential. In a second operation, the controller sets the first interconnect to a fourth potential, the second interconnect to a fifth potential, and the third interconnect to a sixth potential. An absolute value of a difference between the fifth potential and the sixth potential is less than that between the fourth potential and the sixth potential.

公开(公告)号：US20190067311A1

公开(公告)日：2019-02-28

申请号：US16057648

申请日：2018-08-07

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takaumi MORITA

IPC: H01L27/11556 ,  H01L27/11521 ,  G11C16/04 ,  H01L29/66

CPC classification number: H01L27/11556 ,  G11C16/0441 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833

Abstract: A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.

公开(公告)号：US20210090913A1

公开(公告)日：2021-03-25

申请号：US16950389

申请日：2020-11-17

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhito YOSHIMIZU ,  Yuya AKEBOSHI ,  Fuyuma ITO ,  Hakuba KITAGAWA

IPC: H01L21/67 ,  H01L21/3213 ,  H01L21/311

Abstract: According to an embodiment, a substrate treatment apparatus includes a hair member including a noble metal, and a liquid chemical supply member to supply a liquid chemical. While a tip part of the hair member is contact with a predetermined surface of a metal, the liquid chemical is supplied onto the surface of the metal, and the metal is removed with etching.