公开(公告)号：US11233005B1

公开(公告)日：2022-01-25

申请号：US16926447

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/522 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528

Abstract: A method includes providing a fin, an isolation structure, and first and second source/drain (S/D) features over the fin; forming an etch mask covering a first portion and exposing a second portion of the fin; removing the second portion of the fin, resulting in a first trench; filling the first trench with a first dielectric feature; removing the etch mask; and applying etching process(es) to remove the first portion of the fin and to partially recess the first S/D feature. The etching process(es) includes an isotropic etching tuned selective to materials of the first S/D feature and not materials of the isolation structure and the first dielectric feature, resulting in a second trench under the first S/D feature and having a gap between a bottom surface of the first S/D feature and a top surface of the isolation structure. The method further includes forming a via in the second trench.

公开(公告)号：US11211293B2

公开(公告)日：2021-12-28

申请号：US16231613

申请日：2018-12-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Chung-Wei Hsu

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/308 ,  H01L29/423 ,  H01L21/768

Abstract: FinFET device and method of forming the same are provided. The method of forming the FinFET device includes the following steps. A substrate having a plurality of fins is provided. An isolation structure is on the substrate surrounding lower portions of the fins. A hybrid fin is formed aside the fins and on the isolation structure. A plurality of gate lines and a dielectric layer are formed. The gate lines are across the fins and the hybrid fin, the dielectric layer is aside the gate lines. A portion of the gate lines is removed, so as to form first trenches in the dielectric layer and in the gate lines, exposing a portion of the hybrid fin and a portion of the fins underlying the portion of the gate lines. The portion of the fins exposed by the first trench and the substrate underlying thereof are removed, so as to form a second trench under the first trench. An insulating structure is formed in the first trench and the second trench.

公开(公告)号：US11171053B2

公开(公告)日：2021-11-09

申请号：US16422559

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Lin-Yu Huang ,  Huan-Chieh Su ,  Sheng-Tsung Wang ,  Zhi-Chang Lin ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.

公开(公告)号：US20210336019A1

公开(公告)日：2021-10-28

申请号：US17123873

申请日：2020-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Kuo-Cheng Chiang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The second source/drain epitaxial structure has a concave bottom surface.

公开(公告)号：US20210202719A1

公开(公告)日：2021-07-01

申请号：US17194967

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Huan-Chieh Su ,  Ting-Hung Hsu ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234

Abstract: A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.

公开(公告)号：US10950713B2

公开(公告)日：2021-03-16

申请号：US16544196

申请日：2019-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Huan-Chieh Su ,  Ting-Hung Hsu ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234

Abstract: A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.

公开(公告)号：US20200044086A1

公开(公告)日：2020-02-06

申请号：US16218493

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/768 ,  H01L21/28 ,  H01L29/51

Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

公开(公告)号：US10374058B2

公开(公告)日：2019-08-06

申请号：US15706456

申请日：2017-09-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh Su ,  Zhi-Chang Lin ,  Ting-Hung Hsu ,  Jia-Ni Yu ,  Wei-Hao Wu ,  Chih-Hao Wang

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

Abstract: A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes forming a gate electrode layer in a gate trench; filling a recess in the gate electrode layer with a dielectric feature; and etching back the gate electrode layer from top end surfaces of the gate electrode layer while leaving a portion of the gate electrode layer under the dielectric feature.

公开(公告)号：US12224212B2

公开(公告)日：2025-02-11

申请号：US18323907

申请日：2023-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/764 ,  H01L23/528 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

公开(公告)号：US20240395938A1

公开(公告)日：2024-11-28

申请号：US18787223

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.