公开(公告)号：US11728402B2

公开(公告)日：2023-08-15

申请号：US17590409

申请日：2022-02-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L21/306 ,  H01L21/3065

CPC分类号： H01L29/42392 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/4991 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7853 ,  H01L29/78696 ,  H01L21/3065 ,  H01L21/30604

摘要： The present disclosure provides an integrated circuit (IC) device, including: a semiconductor substrate having a top surface; a first source/drain feature and a second source/drain feature disposed on the semiconductor substrate; and a plurality of semiconductor layers including a first semiconductor layer and a second semiconductor layer. Each of the first semiconductor layer and the second semiconductor layer extends longitudinally in a first direction and connects the first source/drain feature and the second source/drain feature. The first semiconductor layer is stacked over the second semiconductor layer in a second direction perpendicular to the first direction. A length of the first semiconductor layer along the first direction is less than a length of the second semiconductor layer along the first direction. The IC device further includes a gate structure engaging center portions of the first semiconductor layer and the second semiconductor layer.

公开(公告)号：US11688791B2

公开(公告)日：2023-06-27

申请号：US16680816

申请日：2019-11-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Jhon Jhy Liaw ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L21/308 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/10

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

摘要： A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.

公开(公告)号：US20230164969A1

公开(公告)日：2023-05-25

申请号：US18151624

申请日：2023-01-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H10B10/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

CPC分类号： H10B10/12 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/41791 ,  H01L27/0886

摘要： Examples of an integrated circuit with a contacting gate structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a memory cell that includes a plurality of fins and a gate extending over a first fin of the plurality of fins and a second fin of the plurality of fins. The gate includes a gate electrode that physically contacts the first fin and a gate dielectric disposed between the gate electrode and the second fin. In some such examples, the first fin includes a source/drain region and a doped region that physically contacts the gate electrode.

公开(公告)号：US20230115015A1

公开(公告)日：2023-04-13

申请号：US18064785

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Jhon Jhy Liaw

IPC分类号： H01L29/78 ,  H01L21/321 ,  H01L29/45 ,  H01L29/40 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/092

摘要： The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

公开(公告)号：US20230081710A1

公开(公告)日：2023-03-16

申请号：US18057688

申请日：2022-11-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L29/06

摘要： Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over the first well. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

公开(公告)号：US11605637B2

公开(公告)日：2023-03-14

申请号：US17345309

申请日：2021-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Jhon Jhy Liaw ,  Min-Chang Liang ,  Ren-Fen Tsui ,  Shih-Chi Fu ,  Yen-Huei Chen

IPC分类号： H01L27/11 ,  G11C11/418 ,  H01L23/528 ,  H01L27/02

摘要： A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

公开(公告)号：US11563087B2

公开(公告)日：2023-01-24

申请号：US17208838

申请日：2021-03-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/10 ,  H01L23/522 ,  H01L27/11 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66

摘要： Fin-based well straps are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin structure doped with a first dopant concentration of the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin structure doped with a second dopant concentration of the first type dopant and second source/drain features of the first type dopant. The second dopant concentration is greater than (for example, at least three times greater than) the first dopant concentration.

公开(公告)号：US20220392904A1

公开(公告)日：2022-12-08

申请号：US17337015

申请日：2021-06-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L27/11 ,  H01L23/528 ,  H01L27/092

摘要： Integrated circuit (“IC”) layouts are disclosed for improving performance of memory arrays, such as static random access memory (“SRAM”). An exemplary IC device includes an SRAM cell and an interconnect structure electrically coupled to the SRAM cell. The interconnect structure includes a first metal layer electrically coupled to the SRAM cell that includes a bit line, a first voltage line having a first voltage, a word line landing pad, and a second voltage line having a second voltage that is different than the first voltage. The first voltage line is adjacent the bit line. The word line landing pad is adjacent the first voltage line. The second voltage line is adjacent the word line landing pad. A second metal layer is disposed over the first metal layer. The second metal layer includes a word line that is electrically coupled to the word line landing pad.

公开(公告)号：US11508737B2

公开(公告)日：2022-11-22

申请号：US16910498

申请日：2020-06-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Kuo-Chiang Ting ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC分类号： H01L27/11 ,  H01L27/11582 ,  H01L49/02 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

摘要： An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

公开(公告)号：US20220359687A1

公开(公告)日：2022-11-10

申请号：US17869743

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

摘要： Gate-all-around (GAA) device and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) device comprises a first nanostructure and a second nanostructure formed on a substrate, wherein each of the first nanostructure and the second nanostructure includes a plurality of semiconductor layers and each of the first nanostructure and the second nanostructure includes a channel region and a source/drain (S/D) region; a first gate structure wrapping the plurality of semiconductor layers of the first nanostructure and a second gate structure wrapping the plurality of semiconductor layers of the second nanostructure; and a S/D contact that contacts at least one of the plurality of semiconductor layers of the first nanostructure and at least one of the plurality of semiconductor layers of the second nanostructure.