公开(公告)号：US20190096888A1

公开(公告)日：2019-03-28

申请号：US15874618

申请日：2018-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting KO ,  Jr-Hung LI ,  Chi On CHUI

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/02 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66

Abstract: Methods of forming a differential layer, such as a Contact Etch Stop Layer (CESL), in a semiconductor device are described herein, along with structures formed by the methods. In an embodiment, a structure includes an active area on a substrate, a gate structure over the active area, a gate spacer along a sidewall of the gate structure, and a differential etch stop layer. The differential etch stop layer has a first portion along a sidewall of the gate spacer and has a second portion over an upper surface of the source/drain region. A first thickness of the first portion is in a direction perpendicular to the sidewall of the gate spacer, and a second thickness of the second portion is in a direction perpendicular to the upper surface of the source/drain region. The second thickness is greater than the first thickness.

公开(公告)号：US20180151683A1

公开(公告)日：2018-05-31

申请号：US15418995

申请日：2017-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yee-Chia YEO ,  Hung-Li CHIANG ,  Jyh-Cherng SHEU ,  Sung-Li WANG ,  I-Sheng CHEN ,  Chi On CHUI

IPC: H01L29/45 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/08 ,  H01L23/522 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/45 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L23/5226 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US20250113551A1

公开(公告)日：2025-04-03

申请号：US18404785

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Sih-Jie LIU ,  Liang-Yin CHEN ,  Chi On CHUI

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A method includes: forming a stack of nanostructures over a substrate; forming a source/drain opening adjacent the stack of nanostructures; forming a semiconductor layer in the source/drain opening; forming an amorphous semiconductor layer by performing an ion implantation on the semiconductor layer; and forming a recrystallized source/drain by annealing the amorphous semiconductor layer.

公开(公告)号：US20230290853A1

公开(公告)日：2023-09-14

申请号：US17836740

申请日：2022-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jin LI ,  Che-Hao CHANG ,  Zhen-Cheng WU ,  Chi On CHUI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/762 ,  H01L21/3115

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L21/76224 ,  H01L21/31155

Abstract: A semiconductor device with doped shallow trench isolation (STI) structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on the fin structure, depositing an oxide liner surrounding the superlattice structure and the fin structure in a first deposition process, forming a dopant source liner on the oxide liner, depositing an oxide fill layer on the dopant source liner in a second deposition process different from the first deposition process, performing a doping process to form a doped oxide liner and a doped oxide fill layer, removing portions of the doped oxide liner, the doped oxide fill layer, and the dopant source liner from sidewalls of the superlattice structure, and forming a gate structure on the fin structure and surrounding the first nanostructured layers.

公开(公告)号：US20230207695A1

公开(公告)日：2023-06-29

申请号：US18175346

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/78391 ,  H01L21/02068 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7851 ,  H01L29/40111 ,  H01L29/66795

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US20230015761A1

公开(公告)日：2023-01-19

申请号：US17875561

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Lung HUNG ,  Ji-Cheng CHEN ,  Weng CHANG ,  Chi On CHUI

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.

公开(公告)号：US20210328065A1

公开(公告)日：2021-10-21

申请号：US17362317

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Bo-Feng YOUNG ,  Chi On CHUI ,  Chih-Yu CHANG ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US20210083120A1

公开(公告)日：2021-03-18

申请号：US16572255

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.

公开(公告)号：US20190067197A1

公开(公告)日：2019-02-28

申请号：US16048957

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Kai-Hsuan LEE ,  Yen-Ming CHEN ,  Chi On CHUI ,  Sai-Hooi YEONG

IPC: H01L23/528 ,  H01L23/532 ,  C23C14/02 ,  H01L21/768 ,  H01L21/288 ,  H01L21/02 ,  C23C16/34 ,  C23C16/04 ,  C23C16/02 ,  C23C14/06 ,  C23C14/04 ,  H01L23/522

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.