公开(公告)号：US11837649B2

公开(公告)日：2023-12-05

申请号：US16939943

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785

Abstract: A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

公开(公告)号：US11784055B2

公开(公告)日：2023-10-10

申请号：US17692824

申请日：2022-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/31 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785 ,  H01L23/3157

Abstract: A method includes following steps. A substrate is etched using a hard mask as an etch mask to form a fin. A bottom anti-reflective coating (BARC) layer is over the fin. A recess is formed in the BARC layer to expose a first portion of the hard mask. A protective coating layer is formed at least on a sidewall of the recess in the BARC layer. A first etching step is performed to remove the first portion of the hard mask to expose a first portion of the fin, while leaving a second portion of the fin covered under the protective coating layer and the BARC layer. A second etching step is performed to lower a top surface of the first portion of the fin to below a top surface of the second portion of the fin.

公开(公告)号：US11769821B2

公开(公告)日：2023-09-26

申请号：US17101291

申请日：2020-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Ping Chen ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

公开(公告)号：US11715779B2

公开(公告)日：2023-08-01

申请号：US17682604

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Chung Chiu ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/66795 ,  H01L27/088

Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

公开(公告)号：US20230154800A1

公开(公告)日：2023-05-18

申请号：US18157352

申请日：2023-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L29/66545 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823468

Abstract: A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.

公开(公告)号：US20220359709A1

公开(公告)日：2022-11-10

申请号：US17813839

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L29/78

Abstract: A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.

公开(公告)号：US20220328356A1

公开(公告)日：2022-10-13

申请号：US17808709

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Che-Cheng Chang ,  Chang-Yin Chen ,  Jr-Jung Lin ,  Chih-Han Lin ,  Yung-Jung Chang

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L27/088 ,  H01L21/3213 ,  H01L29/78

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

公开(公告)号：US20220216322A1

公开(公告)日：2022-07-07

申请号：US17705804

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.

公开(公告)号：US20220181215A1

公开(公告)日：2022-06-09

申请号：US17682621

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/308

Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.

公开(公告)号：US20220173225A1

公开(公告)日：2022-06-02

申请号：US17650942

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.