公开(公告)号：US12261051B2

公开(公告)日：2025-03-25

申请号：US18361464

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/308 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor fin extending from a substrate, and a gate structure extending across the semiconductor fin. From a plan view, the semiconductor fin includes a first sidewall, a second sidewall opposing the first sidewall, an end surface extending along a different direction than the first sidewall and the second sidewall, and a first corner portion connecting the first sidewall and the end surface. The first corner portion is more rounded than the first sidewall and the end surface.

公开(公告)号：US11948835B2

公开(公告)日：2024-04-02

申请号：US17230701

申请日：2021-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/528

CPC classification number: H01L21/76831 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L23/528 ,  H01L21/76804 ,  H01L23/485

Abstract: A device comprises a first metal structure, a dielectric structure, a dielectric residue, and a second metal structure. The dielectric structure is over the first metal structure. The dielectric structure has a stepped sidewall structure. The stepped sidewall structure comprises a lower sidewall and an upper sidewall laterally set back from the lower sidewall. The dielectric residue is embedded in a recessed region in the lower sidewall of the stepped sidewall structure of the dielectric structure. The second metal structure extends through the dielectric structure to the first metal structure.

公开(公告)号：US11854962B2

公开(公告)日：2023-12-26

申请号：US17106766

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/288 ,  H01L23/532 ,  H01L21/027 ,  H01L21/321 ,  H01L29/06

CPC classification number: H01L23/5226 ,  H01L21/0276 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/088 ,  H01L21/3212 ,  H01L21/7684 ,  H01L29/0649

Abstract: A semiconductor device includes a substrate, a bottom etch stop layer over the substrate, a middle etch stop layer over the bottom etch stop layer, and a top etch stop layer over the middle etch stop layer. The top, middle, and bottom etch stop layers include different material compositions from each other. The semiconductor device further includes a dielectric layer over the top etch stop layer and a via extending through the dielectric layer and the top, middle, and bottom etch stop layers. The via has a first sidewall in contact with the dielectric layer and slanted inwardly from top to bottom towards a center of the via and a second sidewall in contact with the bottom etch stop layer and slanted outwardly from top to bottom away from the center of the via.

公开(公告)号：US11784242B2

公开(公告)日：2023-10-10

申请号：US17853104

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Po-Chi Wu ,  Che-Cheng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/66818 ,  H01L21/3065 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/165

Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

公开(公告)号：US11784055B2

公开(公告)日：2023-10-10

申请号：US17692824

申请日：2022-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/31 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785 ,  H01L23/3157

Abstract: A method includes following steps. A substrate is etched using a hard mask as an etch mask to form a fin. A bottom anti-reflective coating (BARC) layer is over the fin. A recess is formed in the BARC layer to expose a first portion of the hard mask. A protective coating layer is formed at least on a sidewall of the recess in the BARC layer. A first etching step is performed to remove the first portion of the hard mask to expose a first portion of the fin, while leaving a second portion of the fin covered under the protective coating layer and the BARC layer. A second etching step is performed to lower a top surface of the first portion of the fin to below a top surface of the second portion of the fin.

公开(公告)号：US20230154800A1

公开(公告)日：2023-05-18

申请号：US18157352

申请日：2023-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L29/66545 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823468

Abstract: A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.

公开(公告)号：US20220328356A1

公开(公告)日：2022-10-13

申请号：US17808709

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Che-Cheng Chang ,  Chang-Yin Chen ,  Jr-Jung Lin ,  Chih-Han Lin ,  Yung-Jung Chang

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L27/088 ,  H01L21/3213 ,  H01L29/78

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

公开(公告)号：US11335681B2

公开(公告)日：2022-05-17

申请号：US16919063

申请日：2020-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/49

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.

公开(公告)号：US11145510B2

公开(公告)日：2021-10-12

申请号：US16666218

申请日：2019-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/225 ,  H01L29/78 ,  H01L29/66 ,  H01L29/36 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device includes a substrate, a FinFET, and an insulating structure. The FinFET includes a fin, a gate electrode, and a gate dielectric layer. The fin is over the substrate. The gate electrode is over the fin. The gate dielectric layer is between the gate electrode and the fin. The insulating structure is over the substrate, adjacent the fin, and has a top surface lower than a top surface of the fin. The top surface of the insulating structure has opposite first and second edge portions and an intermediate portion between the first and second edge portions. The first edge portion of the top surface of the insulating structure is lower than the intermediate portion of the top surface of the insulating structure.

公开(公告)号：US20210313216A1

公开(公告)日：2021-10-07

申请号：US17349741

申请日：2021-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/764 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.