公开(公告)号：US20200004137A1

公开(公告)日：2020-01-02

申请号：US16287450

申请日：2019-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Chin-Hsiang LIN ,  Cheng-I HUANG ,  Chih-Ming LAI ,  Lai Chien WEN ,  Ken-Hsien HSIEH ,  Shih-Ming CHANG ,  Yuan-Te HOU

IPC: G03F1/42 ,  G03F1/50 ,  G03F1/68 ,  G03F7/20

Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.

公开(公告)号：US20190096909A1

公开(公告)日：2019-03-28

申请号：US16022821

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Cheng-Chi CHUANG ,  Chih-Ming LAI ,  Chia-Tien WU ,  Charles Chew-Yuen YOUNG ,  Hui-Ting YANG ,  Jiann-Tyng TZENG ,  Ru-Gun LIU ,  Wei-Cheng LIN ,  Lei-Chun CHOU ,  Wei-An LAI

IPC: H01L27/118 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

公开(公告)号：US20240087896A1

公开(公告)日：2024-03-14

申请号：US18516719

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Min HSIAO ,  Chien-Wen LAI ,  Ru-Gun LIU ,  Chih-Ming LAI ,  Shih-Ming CHANG ,  Yung-Sung YEN ,  Yu-Chen CHANG

IPC: H01L21/033 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/0338 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

公开(公告)号：US20220359203A1

公开(公告)日：2022-11-10

申请号：US17869707

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Min HSIAO ,  Chien-Wen LAI ,  Ru-Gun LIU ,  Chih-Ming LAI ,  Shih-Ming CHANG ,  Yung-Sung YEN ,  Yu-Chen CHANG

IPC: H01L21/033 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/265

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

公开(公告)号：US20210272808A1

公开(公告)日：2021-09-02

申请号：US16806206

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Min HSIAO ,  Chien-Wen LAI ,  Ru-Gun LIU ,  Chih-Ming LAI ,  Shih-Ming CHANG ,  Yung-Sung YEN ,  Yu-Chen CHANG

IPC: H01L21/033 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3115

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

公开(公告)号：US20210082903A1

公开(公告)日：2021-03-18

申请号：US17092100

申请日：2020-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394

Abstract: A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

公开(公告)号：US20200006121A1

公开(公告)日：2020-01-02

申请号：US16374150

申请日：2019-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Chin-Hsiang LIN ,  Chih-Ming LAI ,  Wei-Liang LIN ,  Yung-Sung YEN

IPC: H01L21/768 ,  H01L27/12

Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

公开(公告)号：US20190165177A1

公开(公告)日：2019-05-30

申请号：US16176072

申请日：2018-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Ching-Wei TSAI ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kuo-Cheng CHING ,  Ru-Gun LIU ,  Wei-Hao WU ,  Yi-Hsiung LIN ,  Chia-Hao CHANG ,  Lei-Chun CHOU

IPC: H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20190157085A1

公开(公告)日：2019-05-23

申请号：US16149577

申请日：2018-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming LAI ,  Shih-Ming CHANG ,  Wei-Liang LIN ,  Chin-Yuan TSENG ,  Ru-Gun LIU

IPC: H01L21/033 ,  H01L21/311

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure. The method includes forming third spacers over second sidewalls of the second spacers. The method includes removing the filling layer and the second spacers.

公开(公告)号：US20180166431A1

公开(公告)日：2018-06-14

申请号：US15699990

申请日：2017-09-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng LIN ,  Hui-Ting YANG ,  Shih-Wei PENG ,  Jiann-Tyng TZENG ,  Charles Chew-Yuen YOUNG ,  Chih-Ming LAI

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/088 ,  H01L27/0886

Abstract: A semiconductor device includes at least one first gate strip, at least one second gate strip, at least one first conductive line and at least one first conductive via. An end surface of the at least one first gate strip and an end surface of the at least one second gate strip are opposite each other. The at least one first conductive line is over the at least one first gate strip and the at least one second gate strip and across the end surface of the at least one first gate strip and the end surface of the at least one second gate strip. The at least one first conductive via connects the at least one first conductive line and the at least one first gate strip.