公开(公告)号：US11784222B2

公开(公告)日：2023-10-10

申请号：US17571822

申请日：2022-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chun-An Lin ,  Wei-Yuan Lu ,  Guan-Ren Wang ,  Peng Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

公开(公告)号：US11728397B2

公开(公告)日：2023-08-15

申请号：US17195251

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hung Tsai ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L29/40 ,  H01L29/08

CPC classification number: H01L29/41766 ,  H01L21/32051 ,  H01L21/76831 ,  H01L29/401 ,  H01L29/41791 ,  H01L21/76804 ,  H01L21/76805 ,  H01L23/5226 ,  H01L29/0847

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.

公开(公告)号：US11495606B2

公开(公告)日：2022-11-08

申请号：US17106457

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Po Chang ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Wei-Yang Lee ,  Tzu-Hsiang Hsu

IPC: H01L29/66 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side.

公开(公告)号：US20220328649A1

公开(公告)日：2022-10-13

申请号：US17850393

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Chen ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/40

Abstract: A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

公开(公告)号：US11387331B2

公开(公告)日：2022-07-12

申请号：US16935686

申请日：2020-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting Fang ,  Chung-Hao Cai ,  Jui-Ping Lin ,  Chia-Hsien Yao ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/40 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

公开(公告)号：US11302802B2

公开(公告)日：2022-04-12

申请号：US17085032

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Heng Wang ,  Chun-Han Chen ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/78

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottommost surface of the gate structure is closer to the substrate than a bottommost surface of the source/drain contact.

公开(公告)号：US20210280426A1

公开(公告)日：2021-09-09

申请号：US17328655

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hung Tsai ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

Abstract: A semiconductor structure includes an isolation feature disposed over a semiconductor substrate, a semiconductor fin disposed over the semiconductor substrate and adjacent to the isolation feature, a source/drain (S/D) feature disposed over the semiconductor substrate and apart from the isolation feature, an interlayer dielectric (ILD) layer disposed over the isolation feature and the S/D feature, a first contact plug disposed in the ILD layer and over the isolation feature, a second contact plug disposed in the ILD layer and over the S/D feature, and a dielectric layer between surfaces of the first contact plug and the ILD layer and between a sidewall of the second contact plug and the ILD layer, where a bottom surface of the second contact plug is free of the dielectric layer.

公开(公告)号：US20210257483A1

公开(公告)日：2021-08-19

申请号：US17085032

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Heng Wang ,  Chun-Han Chen ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3213

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottommost surface of the gate structure is closer to the substrate than a bottommost surface of the source/drain contact.

公开(公告)号：US20210175126A1

公开(公告)日：2021-06-10

申请号：US17181217

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chang-Yun Chang ,  Ching-Feng Fu ,  Peng Wang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L27/088 ,  H01L23/522 ,  H01L21/768 ,  H01L23/485 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, first and second fins protruding from the substrate, and first and second source/drain (S/D) features over the first and second fins respectively. The semiconductor device further includes an isolation feature over the substrate and disposed between the first and second S/D features, and a dielectric layer disposed on sidewalls of the first and second S/D features and on sidewalls of the isolation feature. A top portion of the isolation feature extends above the dielectric layer.

公开(公告)号：US11018011B2

公开(公告)日：2021-05-25

申请号：US16366905

申请日：2019-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hung Tsai ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

Abstract: A method includes forming a first trench in an isolation region; forming a second trench in a device region, wherein the device region is disposed adjacent to the isolation region and each of the first and second trenches is disposed between two metal gate structures; forming a first dielectric layer in the first and the second trenches; forming a second dielectric layer over and different from the first dielectric layer; removing a portion of the second dielectric layer from the first and the second trenches, leaving behind a remaining portion of the second dielectric layer in the first trench; removing a portion of the first dielectric layer formed over a bottom surface of the second trench; subsequent to removing the portion of the first dielectric layer, removing the remaining portion of second dielectric layer from the first trench; and forming contact features in the first and the second trenches.