公开(公告)号：US10923659B2

公开(公告)日：2021-02-16

申请号：US16401042

申请日：2019-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Marcus Johannes Henricus van Dal ,  Matthias Passlack

IPC: H01L21/00 ,  H01L51/00 ,  C23C16/455 ,  C23C16/56 ,  H01L23/544 ,  H01L51/05

Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.

公开(公告)号：US20200303530A1

公开(公告)日：2020-09-24

申请号：US16889600

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/775 ,  H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

公开(公告)号：US10679988B2

公开(公告)日：2020-06-09

申请号：US15707682

申请日：2017-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gerben Doornbos ,  Mark Van Dal

IPC: H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from a first isolation insulating layer is formed. A second isolation insulating layer made of different material than the first isolation insulating layer is formed so that a first upper portion of the fin structure is exposed. A dummy gate structure is formed over the exposed first upper portion of the first fin structure. The second isolation insulating layer is etched by using the dummy gate structure as an etching mask. The dummy gate structure is removed so that a gate space is formed. The second isolation insulating layer is etched in the gate space so that a second upper portion of the fin structure is exposed from the first isolation insulating layer. A gate dielectric layer and a gate electrode layer are formed over the exposed second portion of the fin structure.

公开(公告)号：US20200161574A1

公开(公告)日：2020-05-21

申请号：US16590115

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Marcus Johannes Henricus Van Dal ,  Gerben Doornbos

IPC: H01L51/05 ,  H01L27/28 ,  H01L51/10 ,  H01L51/00

Abstract: In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

公开(公告)号：US10170378B2

公开(公告)日：2019-01-01

申请号：US15498748

申请日：2017-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gerben Doornbos ,  Chung-Te Lin ,  Mark Van Dal

IPC: H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device includes first and second nanowire structures disposed on semiconductor substrate extending in first direction on substrate. First nanowire structure includes plurality of first nanowires including first nanowire material extending along first direction and arranged in second direction, second direction substantially perpendicular to first direction. Second nanowire structure includes plurality of second nanowires including second nanowire material extending along first direction arranged in second direction. Second nanowire material is not same as first nanowire material. Each nanowire is spaced-apart from immediately adjacent nanowire. First and second gate structures wrap around first and second nanowires at first region of respective first and second nanowire structures. First and second gate structures include gate electrodes. Viewed in cross section taken along third direction substantially perpendicular to first and second directions, height of first nanowires along second direction is not equal to distance of spacing along second direction between immediately adjacent second nanowires.

公开(公告)号：US20250151370A1

公开(公告)日：2025-05-08

申请号：US19011247

申请日：2025-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gerben Doornbos ,  Marcus Johannes Henricus van Dal ,  Georgios Vellianitis

IPC: H10D64/68 ,  H10B51/30 ,  H10D30/01 ,  H10D30/62 ,  H10D30/67 ,  H10D62/40 ,  H10D62/854

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

公开(公告)号：US11967647B2

公开(公告)日：2024-04-23

申请号：US17361141

申请日：2021-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/786 ,  H01L21/268 ,  H01L21/285 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/268 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66742 ,  H01L29/78696

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes forming conductive plugs in the source/drain contact openings. The method further includes depositing a light blocking layer over the conductive plugs and the at least one dielectric layer. The method further includes etching the light blocking layer to expose the conductive plugs. The method further includes directing a laser irradiation to the conductive plugs and the light blocking layer. The laser irradiation is configured to activate dopants in the source/drain contact regions.

公开(公告)号：US11751487B2

公开(公告)日：2023-09-05

申请号：US16933914

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Mauricio Manfrini

IPC: H10N52/80 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/00

CPC classification number: H10N52/80 ,  H10B61/10 ,  H10N50/85 ,  H10N52/01 ,  H10N52/101

Abstract: A semiconductor device includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

公开(公告)号：US11682587B2

公开(公告)日：2023-06-20

申请号：US17195441

申请日：2021-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark Van Dal ,  Gerben Doornbos

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696 ,  H01L21/0245 ,  H01L29/7831 ,  H01L2029/7858

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.

公开(公告)号：US11302820B2

公开(公告)日：2022-04-12

申请号：US16586790

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/268 ,  H01L21/285 ,  H01L21/324 ,  H01L21/311

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.