公开(公告)号：US09887128B2

公开(公告)日：2018-02-06

申请号：US15276456

申请日：2016-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/311 ,  H01L23/532 ,  H01L21/67 ,  H01L21/764

CPC classification number: H01L21/76825 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/67063 ,  H01L21/67115 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76843 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes forming a first low-k dielectric layer over a substrate; forming a first and second metal features in the first low-k dielectric layer; forming a first trench in the first low-k dielectric layer, the first trench spanning between the first and second metal features; performing a ultraviolet (UV) treatment to sidewalls of the first low-k dielectric layer in the first trench; forming a first etch stop layer in the first trench; and depositing a second low-k dielectric layer on the first etch stop layer, thereby forming an air gap in the first trench.

公开(公告)号：US20230326746A1

公开(公告)日：2023-10-12

申请号：US18326370

申请日：2023-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/3105 ,  H01L29/36 ,  H01L21/266 ,  H01L21/762

CPC classification number: H01L21/0228 ,  H01L27/0886 ,  H01L21/02211 ,  H01L21/823468 ,  H01L21/02208 ,  H01L21/02205 ,  H01L21/31111 ,  H01L21/02126 ,  H01L21/0214 ,  H01L29/6656 ,  H01L21/823431 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/3065 ,  H01L21/823437 ,  H01L29/66545 ,  H01L21/823481 ,  H01L21/31053 ,  H01L29/36 ,  H01L21/266 ,  H01L29/66795 ,  H01L21/76224

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such

公开(公告)号：US20220230871A1

公开(公告)日：2022-07-21

申请号：US17712561

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

公开(公告)号：US20170186683A1

公开(公告)日：2017-06-29

申请号：US15276456

申请日：2016-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin

IPC: H01L23/528 ,  H01L21/67 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76825 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/67063 ,  H01L21/67115 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76843 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes forming a first low-k dielectric layer over a substrate; forming a first and second metal features in the first low-k dielectric layer; forming a first trench in the first low-k dielectric layer, the first trench spanning between the first and second metal features; performing a ultraviolet (UV) treatment to sidewalls of the first low-k dielectric layer in the first trench; forming a first etch stop layer in the first trench; and depositing a second low-k dielectric layer on the first etch stop layer, thereby forming an air gap in the first trench.

公开(公告)号：US20240387332A1

公开(公告)日：2024-11-21

申请号：US18786724

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin

IPC: H01L23/482 ,  H01L21/762

Abstract: A device includes a first conductive feature in an insulating layer; a dielectric layer over the first conductive feature; a second conductive feature in the dielectric layer, wherein the second conductive feature is over and physically contacting the first conductive feature; an air spacer encircling the second conductive feature, wherein sidewalls of the second conductive feature are exposed to the air spacer; a metal cap covering the second conductive feature and extending over the air spacer, wherein the air spacer is sealed by a bottom surface of the metal cap; a first etch stop layer on the dielectric layer, wherein a sidewall of the first etch stop layer physically contacts a sidewall of the metal cap; and a second etch stop layer extending on a top surface of the metal cap and a top surface of the first etch stop layer.

公开(公告)号：US11705327B2

公开(公告)日：2023-07-18

申请号：US17712561

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/36

CPC classification number: H01L21/0228 ,  H01L21/0214 ,  H01L21/02126 ,  H01L21/02205 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/31111 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/6656 ,  H01L21/266 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/66795

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

公开(公告)号：US11295948B2

公开(公告)日：2022-04-05

申请号：US17201691

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/36

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

公开(公告)号：US10304677B2

公开(公告)日：2019-05-28

申请号：US15952895

申请日：2018-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/36

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

公开(公告)号：US20150252475A1

公开(公告)日：2015-09-10

申请号：US14202308

申请日：2014-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin ,  Chia-Ho Chen

IPC: C23C16/458 ,  C23C16/46 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/285 ,  C23C16/455 ,  C23C16/44

CPC classification number: H01L21/28506 ,  C23C16/45519 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/4558 ,  C23C16/45591

Abstract: The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a gas delivery ring with an outlet disposed under the gas import. A pressure near the outlet of the gas delivery ring is smaller than that of the rest of the vacuum chamber.

Abstract translation: 本公开涉及一种化学气相沉积装置及其相关方法。 在一些实施例中，CVD装置具有真空室和具有气体导入轴的气体进口，通过该进气轴将处理气体输入到真空室中并且布置在真空室的上部区域附近。 至少一个排气口设置在真空室的底部区域附近。 CVD设备还具有气体输送环，气体输送环具有设置在气体输入下的出口。 气体输送环出口附近的压力小于真空室其余部分的压力。