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    NON-TRANSITORY COMPUTER-READABLE MEDIUM, INTEGRATED CIRCUIT DEVICE AND METHOD
    12.
    发明公开
    NON-TRANSITORY COMPUTER-READABLE MEDIUM, INTEGRATED CIRCUIT DEVICE AND METHOD 审中-公开

    公开(公告)号：US20230154917A1

    公开(公告)日：2023-05-18

    申请号：US18156605

    申请日：2023-01-19

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chih-Liang CHEN ,  Shun Li CHEN ,  Li-Chun TIEN ,  Ting Yu CHEN ,  Hui-Zhong ZHUANG

    IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092

    CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L27/092

    Abstract: A non-transitory computer-readable medium contains thereon a cell library. The cell library includes a plurality of cells configured to be placed in a layout diagram of an integrated circuit (IC). Each cell among the plurality of cells includes a first active region inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region overlaps the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region. The plurality of cells includes at least one cell a width of which in the first direction is equal to one gate region pitch between adjacent gate regions of the IC.

    MULTI-BIT STRUCTURE
    13.
    发明申请
    MULTI-BIT STRUCTURE 有权

    公开(公告)号：US20220367440A1

    公开(公告)日：2022-11-17

    申请号：US17876909

    申请日：2022-07-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Shao-Lun CHIEN ,  Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

    IPC: H01L27/02 ,  G06F30/392 ,  H01L23/522

    Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

    DOUBLE RULE INTEGRATED CIRCUIT LAYOUTS FOR A DUAL TRANSMISSION GATE
    15.
    发明申请
    DOUBLE RULE INTEGRATED CIRCUIT LAYOUTS FOR A DUAL TRANSMISSION GATE 有权

    公开(公告)号：US20210098453A1

    公开(公告)日：2021-04-01

    申请号：US17120839

    申请日：2020-12-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Wei PENG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Li-Chun TIEN ,  Pin-Dai SUE ,  Wei-Cheng LIN

    IPC: H01L27/092 ,  H03K17/687

    Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

    INTEGRATED CIRCUIT
    16.
    发明申请
    INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200328201A1

    公开(公告)日：2020-10-15

    申请号：US16837970

    申请日：2020-04-01

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jian-Sing LI ,  Guo-Huei WU ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

    IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  G06F30/392

    Abstract: An integrated circuit includes a first cell and a second cell. The first cell with a first cell height along a first direction includes a first active region and a second active region that extend in a second direction different from the first direction. The first active region overlaps the second active region in a layout view. The second cell with a second cell height includes a first plurality of active regions and a second plurality of active regions. The first plurality of active regions and the second plurality of active regions extend in the second direction and the first plurality of active regions overlap the second plurality of active regions, respectively, in the layout view. The first cell abuts the second cell, and the first active region is aligned with one of the first plurality of active regions in the layout view.

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