公开(公告)号：US20220271026A1

公开(公告)日：2022-08-25

申请号：US17181196

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tao Yi Hung ,  Yu-Xuan Huang ,  Kuo-Ji Chen

IPC: H01L27/02 ,  H01L23/528

Abstract: An ESD protection device includes a PN diode formed in a semiconductor body. The PN diode has a first contact coupled to a metal structure on a front side of the semiconductor body and a second contact coupled to a metal structure on a back side of the semiconductor body. The metal coupled to the first contact is spaced apart from the metal coupled to the second contact by a thickness of the semiconductor body. This spacing greatly reduces the capacitance associated with the metal structures, which can substantially reduce the overall capacitance added to an I/O channel by the ESD protection device and thereby improve the performance of a high-speed circuit that uses the I/O channel.

公开(公告)号：US10741543B2

公开(公告)日：2020-08-11

申请号：US16105494

申请日：2018-08-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Heng Chang ,  Kuo-Ji Chen ,  Ming-Hsiang Song

IPC: H01L27/02 ,  H01L27/088

Abstract: A device includes an integrated circuit including a single standard cell that is selected from a standard cell library used for design of the layout of the integrated circuit. The single standard cell includes a first active region, a second active region, a first gate, a second gate, and a third gate. The first gate is arranged over the first active region, for formation of at least one first electrostatic discharge (ESD) protection component. The second gate is separate from the first gate, and the second gate is arranged over the second active region, for formation of at least one second ESD protection component. The third gate is separate from the first gate and the second gate, and the third gate is arranged over the first active region and the second active region, for formation of at least one transistor.

公开(公告)号：US09082623B2

公开(公告)日：2015-07-14

申请号：US14106936

申请日：2013-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yi Yang ,  Kuo-Ji Chen ,  Chien-Yuan Lee

IPC: H01L29/76 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0288 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device.

Abstract translation: FinFET器件包括形成在多电平互连半导体器件中的对应的多个鳍片上的多个FinFET器件。 每个源极和每个漏极通过位于最低互连电平以下的金属电阻元件耦合到金属互连电平。 在一个实施例中，在多个翅片上延伸的金属段包括到每个翅片的触点，从而提供不同长度的下面的金属电阻元件。 多个翅片和下面的金属段被布置成使得每个FinFET器件具有由源极和漏极金属电阻元件提供的相同的总电阻，即使与鳍片相关联的源极金属电阻元件和漏极金属电阻元件可具有 不同长度 该布置为每个FinFET器件提供相同的导通电阻和相同的ESD故障电流。

公开(公告)号：US09026973B2

公开(公告)日：2015-05-05

申请号：US13888405

申请日：2013-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chun Tien ,  Chen-Chi Wu ,  Kuo-Ji Chen

IPC: G06F17/50 ,  H01L21/033

CPC classification number: G06F17/50 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/0337 ,  H01L23/5223 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first conductive structure and the second conductive structure. The peacekeeper structure is separated from at least one of the first conductive structure and the second conductive structure by a fixed spacing distance for conductive lines for a self-aligned double patterning (“SADP”) process from the integrated circuit was formed.

Abstract translation: 一种集成电路包括被配置为具有第一电压电位的器件的第一导电结构，该器件的第二导电结构被配置为具有不同于第一电压电位的第二电压电位，以及设置在并分离之间的维持和平结构 第一导电结构和第二导电结构。 维持和平结构与第一导电结构和第二导电结构中的至少一个分离，形成用于自对准双图案化（“SADP”）工艺的导线的固定间隔距离。

公开(公告)号：US12125809B2

公开(公告)日：2024-10-22

申请号：US17239215

申请日：2021-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yu Ma ,  Hui-Mei Chou ,  Kuo-Ji Chen

IPC: H01L23/58 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L23/585 ,  H01L23/522 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming signal lines in a pair of neighboring metal layers of a semiconductor device, and forming first dummy conductive cells in an empty area without metal lines passing therethrough, between the pair of neighboring metal layers. At least two dummy conductive cells of the first dummy conductive cells that are separated from each other, and the at least two dummy conductive cells fully overlap one of the signal lines in plan view.

公开(公告)号：US12033962B2

公开(公告)日：2024-07-09

申请号：US18232739

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

IPC: H01L23/60 ,  H01L27/02 ,  H02H9/04

CPC classification number: H01L23/60 ,  H01L27/0266 ,  H01L27/0292 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

公开(公告)号：US11973075B2

公开(公告)日：2024-04-30

申请号：US17181196

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tao Yi Hung ,  Yu-Xuan Huang ,  Kuo-Ji Chen

IPC: H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0255 ,  H01L23/5286 ,  H01L27/0292

Abstract: An ESD protection device includes a PN diode formed in a semiconductor body. The PN diode has a first contact coupled to a metal structure on a front side of the semiconductor body and a second contact coupled to a metal structure on a back side of the semiconductor body. The metal coupled to the first contact is spaced apart from the metal coupled to the second contact by a thickness of the semiconductor body. This spacing greatly reduces the capacitance associated with the metal structures, which can substantially reduce the overall capacitance added to an I/O channel by the ESD protection device and thereby improve the performance of a high-speed circuit that uses the I/O channel.

公开(公告)号：US11935885B2

公开(公告)日：2024-03-19

申请号：US18066060

申请日：2022-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Heng Chang ,  Kuo-Ji Chen ,  Ming-Hsiang Song

IPC: H01L27/08 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0274 ,  H01L27/0207 ,  H01L27/0266 ,  H01L27/0292 ,  H01L27/0296 ,  H01L27/0886

Abstract: A device includes standard cells in a layout of an integrated circuit. The standard cells include a first standard cell and a second standard cell disposed next to each other. The first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and includes a first gate and a second gate. The first gate includes a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively. The second gate is separate from the first gate. The second gate includes a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively. The first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.

公开(公告)号：US11817403B2

公开(公告)日：2023-11-14

申请号：US17199299

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

IPC: H01L23/60 ,  H01L27/02 ,  H02H9/04

CPC classification number: H01L23/60 ,  H01L27/0266 ,  H01L27/0292 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

公开(公告)号：US12027525B2

公开(公告)日：2024-07-02

申请号：US16940930

申请日：2020-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien Yao Huang ,  Wun-Jie Lin ,  Kuo-Ji Chen

IPC: H01L27/11 ,  G06F30/392 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/118 ,  G06F117/02

CPC classification number: H01L27/11807 ,  G06F30/392 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/0207 ,  G06F2117/02 ,  H01L2027/1189

Abstract: An integrated circuit (IC) device includes a plurality of TAP cells arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of TAP cells includes at least one first TAP cell. The first TAP cell includes two first end areas and a first middle area arranged consecutively in the second direction. The first middle area includes a first dopant of a first type implanted in a first well region of the first type. The first end areas are arranged on opposite sides of the first middle area in the second direction. Each of the first end areas includes a second dopant of a second type implanted in the first well region, the second type different from the first type.