公开(公告)号：US20230354600A1

公开(公告)日：2023-11-02

申请号：US18346056

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wei Cheng WU

IPC: H10B41/47 ,  H01L29/423 ,  H01L21/285 ,  H01L29/788 ,  H01L21/306 ,  H01L29/66 ,  H10B41/30 ,  H10B99/00

CPC classification number: H10B41/47 ,  H01L29/42328 ,  H01L21/28518 ,  H01L29/788 ,  H01L21/30625 ,  H01L29/66825 ,  H10B41/30 ,  H10B99/00

Abstract: A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

公开(公告)号：US20220406662A1

公开(公告)日：2022-12-22

申请号：US17815180

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wen-Tuo HUANG ,  Yong-Shiuan TSAIR

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28

Abstract: The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

公开(公告)号：US20210343734A1

公开(公告)日：2021-11-04

申请号：US17374591

申请日：2021-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wei Cheng WU

IPC: H01L27/11521 ,  H01L27/11526

Abstract: A device has a semiconductor substrate including a recessed region. The recessed region has a center portion and a periphery portion. An isolation region abuts the periphery portion. A plurality of gate stacks are in the recessed region. A protective layer overlying the plurality of gate stacks and the isolation region has a substantially planar upper surface across the recessed region and the isolation region.

公开(公告)号：US20210343733A1

公开(公告)日：2021-11-04

申请号：US17374573

申请日：2021-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wei Cheng WU

IPC: H01L27/11521 ,  H01L27/11526

Abstract: A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.

公开(公告)号：US20210134678A1

公开(公告)日：2021-05-06

申请号：US16938875

申请日：2020-07-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Te-An CHEN ,  Meng-Han LIN

IPC: H01L21/8234 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78

Abstract: In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.

公开(公告)号：US20210057406A1

公开(公告)日：2021-02-25

申请号：US16549077

申请日：2019-08-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Wen-Tuo HUANG ,  Yong-Shiuan TSAIR

IPC: H01L27/06 ,  H01L21/8234

Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate haying spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

公开(公告)号：US20200266196A1

公开(公告)日：2020-08-20

申请号：US16866506

申请日：2020-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L27/11575 ,  H01L27/11526 ,  H01L27/11546 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/761 ,  H01L21/266

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US20170054037A1

公开(公告)日：2017-02-23

申请号：US15346501

申请日：2016-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chieh-Chih CHOU ,  Chih-Wen HSIUNG ,  Kong-Beng THEI

IPC: H01L29/872 ,  H01L21/762 ,  H01L29/66 ,  H01L21/324 ,  H01L21/225 ,  H01L21/285 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/872 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/66143

Abstract: A Schottky barrier diode is provided, which includes a semiconductor substrate, a first well region, an isolation region, a silicide layer and a silicon oxide-containing layer. The first well region of a first conductivity type is in the semiconductor substrate. The isolation region is in the first well region. The silicide layer is laterally adjacent to the isolation region, and over and in contact with the first well region. The silicon oxide-containing layer is over and in contact with the isolation region.

Abstract translation: 提供一种肖特基势垒二极管，其包括半导体衬底，第一阱区，隔离区，硅化物层和含氧化硅的层。 第一导电类型的第一阱区位于半导体衬底中。 隔离区位于第一阱区。 硅化物层横向邻近隔离区域，并且与第一阱区域接触并接触。 含氧化硅的层在隔离区上方并且接触。

公开(公告)号：US20240047219A1

公开(公告)日：2024-02-08

申请号：US18488505

申请日：2023-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chih-Pin HUANG ,  Ching-Wen CHAN

IPC: H01L21/3105 ,  H01L21/308 ,  H01L21/762 ,  H10B41/30

CPC classification number: H01L21/31056 ,  H01L21/3086 ,  H01L21/76283 ,  H10B41/30

Abstract: An integrated circuit device includes a substrate, an isolation feature, a memory cell, and a semiconductor device. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. The isolation feature is in the transition region. A top surface of the isolation feature has a first portion and a second portion lower than the first portion, the second portion of the top surface of the isolation feature is between the cell region and the first portion of the top surface of the isolation feature, and a bottom surface of the isolation feature has a step height directly below the second portion of the top surface of the isolation feature. The is memory cell over the cell region of the substrate. The semiconductor device is over the peripheral region of the substrate.

公开(公告)号：US20220139718A1

公开(公告)日：2022-05-05

申请号：US17574414

申请日：2022-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chih-Pin HUANG ,  Ching-Wen CHAN

IPC: H01L21/3105 ,  H01L27/11521 ,  H01L21/308 ,  H01L21/762

Abstract: An integrated circuit device includes a substrate, a first isolation feature, a memory cell, and a semiconductor device. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. The first isolation feature is in the transition region. The substrate includes a protrusion portion between a first portion and a second portion of the first isolation feature, the second portion is between the first portion and the cell region, and a top surface of the first portion of the first isolation feature has a first part and a second part lower than the first part, and the second part is between the first part and the second portion of the first isolation feature. The memory cell is over the cell region of the substrate. The semiconductor device is over the peripheral region of the substrate.